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TLV809K33 Datasheet(PDF) 4 Page - Texas Instruments |
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TLV809K33 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 20 page  4 TLV809 SLVSA03D – JUNE 2010 – REVISED MARCH 2016 www.ti.com Product Folder Links: TLV809 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 7.3 Recommended Operating Conditions at specified temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage 2 6 V CIN VDD bypass capacitor 0.1 µF TA Operating free-air temperature range –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.4 Thermal Information THERMAL METRIC(1) TLV809 UNIT DBV (SOT-23) DBZ (SOT-23) 3 PINS 3 PINS RθJA Junction-to-ambient thermal resistance 242.1 286.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 213.0 105.6 °C/W RθJB Junction-to-board thermal resistance 123.4 124.4 °C/W ψJT Junction-to-top characterization parameter 45.7 25.8 °C/W ψJB Junction-to-board characterization parameter 130.9 107.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W (1) The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 ms/V. (2) To ensure best stability of the threshold voltage, place a bypass capacitor ( 0.1-µF ceramic) near the supply pins. 7.5 Electrical Characteristics at TA = –40°C to +85°C (unless otherwise noted); typical values are at TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage VDD = 2.5 V to 6 V, IOH = –500 µA VDD – 0.2 V VDD = 3.3 V, IOH = –2 mA VDD – 0.4 VDD = 6 V, IOH = –4 mA VDD – 0.4 VOL Low-level output voltage VDD = 2 V to 6 V, IOH = 500 µA 0.2 V VDD = 3.3 V, IOH = 2 mA 0.4 VDD = 6 V, IOH = 4 mA 0.4 Power-up reset voltage(1) VDD ≥ 1.1 V, IOL = 50 µA 0.2 V VIT– Negative-going input threshold voltage(2) TLV809J25 TA = –40°C to +85°C 2.20 2.25 2.30 V TLV809L30 2.58 2.64 2.70 TLV809K33 2.87 2.93 2.99 TLV809I50 4.45 4.55 4.65 Vhys Hysteresis TLV809J25 30 mV TLV809L30 35 TLV809K33 40 TLV809I50 60 IDD Supply current VDD = 2 V, RESET is unconnected 9 12 µA VDD = 6 V, RESET is unconnected 20 25 CI Input capacitance VI = 0 V to VDD 5 pF |
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