Electronic Components Datasheet Search |
|
AD6672BCPZ-250 Datasheet(PDF) 11 Page - Analog Devices |
|
AD6672BCPZ-250 Datasheet(HTML) 11 Page - Analog Devices |
11 / 30 page Data Sheet AD6672 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 24 CSB 23 SCLK 22 SDIO 21 DCO+ 20 DCO– 19 D9+/D10+ (MSB) 18 D9–/D10– (MSB) 17 DRVDD 1 2 3 4 5 6 7 8 CLK+ CLK– AVDD OR– OR+ 0/D0– (LSB) 0/D0+ (LSB) DRVDD AD6672 INTERLEAVED LVDS TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 2. DNC = NO NOT CONNECT. DO NOT CONNECT TO THIS PIN. Figure 3. LFCSP Pin Configuration (Top View) Table 8. Pin Function Descriptions Pin No. Mnemonic Type Description ADC Power Supplies 8, 17 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 3, 27, 28, 31, 32 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND, Exposed Paddle Ground Analog Ground. The exposed thermal paddle on the bottom of the package provides the analog ground for the part. This exposed paddle must be connected to ground for proper operation. 25 DNC Do Not Connect. Do not connect to this pin. ADC Analog 30 VIN+ Input Differential Analog Input Pin (+). 29 VIN− Input Differential Analog Input Pin (−). 26 VCM Output Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to ground using a 0.1 μF capacitor. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Outputs 5 OR+ Output Overrange indicator—True. 4 OR− Output Overrange indicator—Complement. 7 0/D0+ (LSB) Output DDR LVDS Output Data 0—True. The output bit on the rising edge of the data clock output (DCO) from this output is always a Logic 0 (see Figure 2). 6 0/D0− (LSB) Output DDR LVDS Output Data 0—Complement. The output bit on the rising edge of the data clock output (DCO) from this output is always a Logic 0 (see Figure 2). 10 D1+/D2+ Output DDR LVDS Output Data 1/2—True. 9 D1−/D2− Output DDR LVDS Output Data 1/2—Complement. 12 D3+/D4+ Output DDR LVDS Output Data 3/4—True. 11 D3−/D4− Output DDR LVDS Output Data 3/4—Complement. 14 D5+/D6+ Output DDR LVDS Output Data 5/6—True. 13 D5−/D6− Output DDR LVDS Output Data 5/6—Complement. 16 D7+/D8+ Output DDR LVDS Output Data 7/8—True. 15 D7−/D8− Output DDR LVDS Output Data 7/8—Complement. 19 D9+/D10+ (MSB) Output DDR LVDS Output Data 9/10—True. 18 D9−/D10− (MSB) Output DDR LVDS Output Data 9/10—Complement. 21 DCO+ Output LVDS Data Clock Output—True. 20 DCO− Output LVDS Data Clock Output—Complement. SPI Control 23 SCLK Input SPI Serial Clock. 22 SDIO Input/output SPI Serial Data I/O. 24 CSB Input SPI Chip Select (Active Low). Rev. C | Page 11 of 30 |
Similar Part No. - AD6672BCPZ-250 |
|
Similar Description - AD6672BCPZ-250 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |