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TUSB3210 Datasheet(PDF) 3 Page - Texas Instruments |
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TUSB3210 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 44 page iii Contents Section Title Page 1 Introduction 1–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features 1–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Functional Block Diagram 1–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Terminal Assignments 1–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Ordering Information 1–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Terminal Functions 1–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional Description 2–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 MCU Memory Map 2–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Miscellaneous Registers 2–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 TUSB3210 Boot Operation 2–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 MCNFG: MCU Configuration Register 2–3 . . . . . . . . . . . . . . . . . 2.2.3 PUR_n: GPIO Pullup Register for Port n (n = 0 to 3) 2–3 . . . . . 2.2.4 INTCFG: Interrupt Configuration 2–3 . . . . . . . . . . . . . . . . . . . . . . 2.2.5 WDCSR: Watchdog Timer, Control, and Status Register 2–4 . 2.2.6 PCON: Power Control Register (at SFR 87h) 2–4 . . . . . . . . . . . 2.3 Buffers + I/O RAM Map 2–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Endpoint Descriptor Block (EDB-1 to EDB-3) 2–7 . . . . . . . . . . . . . . . . . . . . 2.4.1 OEPCNF_n: Output Endpoint Configuration 2–7 . . . . . . . . . . . 2.4.2 OEPBBAX_n: Output Endpoint X-Buffer Base-Address 2–8 . . 2.4.3 OEPBCTX_n: Output Endpoint X Byte Count 2–8 . . . . . . . . . . 2.4.4 OEPBBAY_n: Output Endpoint Y-Buffer Base-Address 2–8 . . 2.4.5 OEPBCTY_n: Output Endpoint Y Byte Count 2–8 . . . . . . . . . . . 2.4.6 OEPSIZXY_n: Output Endpoint X/Y Byte Count 2–9 . . . . . . . . 2.4.7 IEPCNF_n: Input Endpoint Configuration 2–9 . . . . . . . . . . . . . . 2.4.8 IEPBBAX_n: Input Endpoint X-Buffer Base-Address 2–9 . . . . . 2.4.9 IEPBCTX_n: Input Endpoint X-Byte Base-Address 2–10 . . . . . . 2.4.10 IEPBBAY_n: Input Endpoint Y-Buffer Base-Address 2–10 . . . . . 2.4.11 IEPBCTY_n: Input Endpoint Y Byte Count 2–10 . . . . . . . . . . . . . 2.4.12 IEPSIZXY_n: Input Endpoint X/Y-Buffer Size 2–11 . . . . . . . . . . . 2.5 Endpoint-0 Descriptor Registers 2–11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 IEPCNFG_0: Input Endpoint-0 Configuration Register 2–11 . . . 2.5.2 IEPBCNT_0: Input Endpoint-0 Byte Count Register 2–12 . . . . . 2.5.3 OEPCNFG_0: Output Endpoint-0 Configuration Register 2–12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 OEPBCNT_0: Output Endpoint-0 Byte Count Register 2–13 . . . 2.6 USB Registers 2–13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 FUNADR: Function Address Register 2–13 . . . . . . . . . . . . . . . . . |
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