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BQ29701DSER Datasheet(PDF) 5 Page - Texas Instruments |
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BQ29701DSER Datasheet(HTML) 5 Page - Texas Instruments |
5 / 31 page 5 bq2970, bq2971, bq2972, bq2973 www.ti.com SLUSBU9C – MARCH 2014 – REVISED MARCH 2016 Product Folder Links: bq2970 bq2971 bq2972 bq2973 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7 Specifications 7.1 Absolute Maximum Ratings (1) MIN MAX UNIT Supply control and input Input voltage: BAT –0.3 12 V V– pin(pack–) BAT – 28 BAT + 0.3 V FET drive and protection DOUT (Discharge FET Output), GDSG (Discharge FET Gate Drive) VSS – 0.3 BAT + 0.3 V COUT (Charge FET Output), GCHG (Charge FET Gate Drive) BAT – 28 BAT + 0.3 V Operating temperature: TFUNC –40 85 °C Storage temperature, Tstg –55 150 °C (1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges into the device. (2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 1000 V may have higher performance. (3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may have higher performance. 7.2 ESD Ratings VALUE UNIT VESD (1) Electrostatic Discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(3) ±500 (1) For more information about traditional and new thermal metrics, see the IC package Thermal Metrics application report, SPRA953. 7.3 Recommended Operating Conditions (1) MIN MAX UNIT Supply control and input Positive input voltage: BAT –0.3 8 V Negative input voltage: V– BAT – 25 BAT V FET drive and protection Discharge FET control: DOUT VSS BAT V Charge FET control: COUT BAT – 25 BAT V Temperature Ratings Operating temperature: TAmb –40 85 °C Storage temperature: TS –55 150 °C Lead temperature (soldering 10 s) 300 °C Thermal resistance junction to ambient, θJA (1) 250 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 7.4 Thermal Information THERMAL METRIC(1) bq297xx UNIT DSE (WSON) 12 PINS RθJA, High K Junction-to-ambient thermal resistance(2) 190.5 °C/W RθJC(top) Junction-to-case(top) thermal resistance(3) 94.9 °C/W RθJB Junction-to-board thermal resistance(4) 149.3 °C/W |
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