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SK100ELT21WD Datasheet(PDF) 1 Page - Semtech Corporation |
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SK100ELT21WD Datasheet(HTML) 1 Page - Semtech Corporation |
1 / 5 page HIGH-PERFORMANCE PRODUCTS 1 www.semtech.com Revision 1/October 16, 2001 SK10/100ELT21W Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator Description Features Functional Block Diagram PIN Names The SK10/100ELT21W is a single differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator. Since PECL (Positive ECL) levels are used, only +VCC and ground are required. The small outline, 8 lead SOIC package, low skew, and the single gate design of the SK10/100ELT21W makes it ideal for applications which require the translation of a clock and a data signal. Unlike the TTL totem pole outputs, the outputs of the ELT21W can be interfaced directly to CMOS inputs with better VOH (VCC – 0.5V) levels. With extended supply voltage capability, the device is functionally compatible with MC10/100ELT21 (5V) and MC10/100LVELT21 (3.3V). • Extended Supply Voltage Range (VCC = +3.0V to 5.5V) • 2.4 ns Typical Propagation Delay • Differential PECL Inputs • True Complementary CMOS/TTL Output • Flow Through Pinouts • Functionally compatible with MC10/100ELT21 and MC10/100LVELT21 • 75K W Internal Input Pulldown Resistors • Specified Over Industrial Temperature Range: –40oC to 85oC • ESD Protection of >4000V • Small Outline 8 Lead SOIC (150 mils) Package • Flammability Rate: UL-94 code V-0 • Moisture Sensitivity: Level 1 n i Pn o i t c n u F O Qt u p t u O L T T / S O M C * 0 D , 0 D B B V s t u p n I L C E P l a i t n e r e f f i D t u p t u O e g a t l o V d e c n e r e f e R V C C V + C C y l p p u S D N G C N d n u o r G t c e n n o C o N 1 2 3 4 D0* NC D0 VBB 8 7 6 5 VCC Q0 NC GND TTL PECL |
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