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ATTINY28L-4PI Datasheet(PDF) 10 Page - ATMEL Corporation |
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ATTINY28L-4PI Datasheet(HTML) 10 Page - ATMEL Corporation |
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10 / 75 page  10 ATtiny28L/V 1062E–10/01 Subroutine and Interrupt Hardware Stack The ATtiny28 uses a 3-level-deep hardware stack for subroutines and interrupts. The hardware stack is 10 bits wide and stores the program counter (PC) return address while subroutines and interrupts are executed. RCALL instructions and interrupts push the PC return address onto stack level 0, and the data in the other stack levels 1 - 2 are pushed one level deeper in the stack. When a RET or RETI instruction is executed the returning PC is fetched from stack level 0, and the data in the other stack levels 1 - 2 are popped one level in the stack. If more than three subsequent subroutine calls or interrupts are executed, the first val- ues written to the stack are overwritten. Memory Access and Instruction Execution Timing This section describes the general access timing concepts for instruction execution and internal memory access. The AVR CPU is driven by the System Clock, directly generated from the external clock crystal for the chip. No internal clock division is used. Figure 13 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipe- lining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks and functions per power unit. Figure 13. The Parallel Instruction Fetches and Instruction Executions Figure 14 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 14. Single Cycle ALU Operation System Clock Ø 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch T1 T2 T3 T4 System Clock Ø Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back T1 T2 T3 T4 |
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