ICS1524 datasheet(3/24 Pages) ICST

Part #	ICS1524

Description	Dual Output Phase Controlled SSTL-3/PECL Clock Generator

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Manufacturer	ICST [Integrated Circuit Systems]

Direct Link	http://www.icst.com

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ICS1524 Block Diagram

June 25, 2001

Charge

Pump

Phase/

Freq

Detector

VCO

Post-

Scaler

Divider

EXTFIL (8)

Ref_Pol

Reg 0:2

HSYNC

(7)

EXTFB

(6)

MUX

Fbk_Sel

Reg 0:4

DPACLK+ (21)

DPACLK– (20)

DPACLK (17)

FUNC (15)

I2C

Interface

Power-

On

Reset

SCL

(4)

SDA

(3)

CLK+ (23)

CLK– (22)

MUX

Func_Sel

Reg 0:5

CLK (16)

MUX

OSC

(12)

Osc

Divider

XFILRET (9)

I2CADR

(13)

Lock

Logic

PECL

Bias

IREF

(24)

Int Filter

LOCK/REF (14)

Filter

Select

DPA_Lock

Reg 12:0

PFD

Reg 1:0-2

PLL_Lock

Reg 12:1

En_DLS

Reg 0:7

En_PLS

Reg 0:6

PD_Pol

Reg 0:1

Osc_Div

Reg 7:0-6

PSD

Reg 1:4-5

Fil_Sel

Reg 4:7

DPA_OS

Reg 4:0-5

Reg

OE_F

Reg 6:4

6

:

OE_P2

Reg 2

Reg

OE_T2

6:3

OE-Pck

Reg 6:0

OE_Tck

Reg 6:1

Feedback

Divider

FDB0

2:0-7

FDB1

Reg: 3:0-3

Fbk_Pol

Reg 0:3

DPA_Res

Reg 5:0-1

0

1

0

1

0

1

+

Dynamic

Phase

Adjust

PDEN (5)

Ck2_Inv

Reg 6:5

MUX

0

1

Output

Scaler

Out_Scl

Reg 6:6-7

PDen

Reg 0:0

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ICS1524 Datasheet(PDF) 3 Page - Integrated Circuit Systems

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