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HD6475368RCG Datasheet(PDF) 5 Page - Hitachi Semiconductor |
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HD6475368RCG Datasheet(HTML) 5 Page - Hitachi Semiconductor |
5 / 487 page 4.8.2 Disabling of Exceptions Immediately after a Reset ··················································92 4.8.3 Disabling of Interrupts after a Data Transfer Cycle ··················································92 4.9 Stack Status after Completion of Exception Handling ························································93 4.9.1 PC Value Pushed on Stack for Trace, Interrupts, Trap Instructions, and Zero Divide Exceptions ·······································95 4.9.2 PC Value Pushed on Stack for Address Error and Invalid Instruction Exceptions ······························································································95 4.10 Notes on Use of the Stack ····································································································95 Section 5 Interrupt Controller 5.1 Overview ······························································································································97 5.1.1 Features ·····················································································································97 5.1.2 Block Diagram ··········································································································98 5.1.3 Register Configuration ······························································································99 5.2 Interrupt Types ·····················································································································99 5.2.1 External Interrupts ····································································································99 5.2.2 Internal Interrupts ····································································································101 5.2.3 Interrupt Vector Table ·····························································································102 5.3 Register Descriptions ·········································································································104 5.3.1 Interrupt Priority Registers A to F (IPRA to IPRF) ················································104 5.3.2 Timing of Priority Setting ·······················································································105 5.4 Interrupt Handling Sequence ·····························································································105 5.4.1 Interrupt Handling Flow ·························································································105 5.4.2 Stack Status after Interrupt Handling Sequence ·····················································108 5.4.3 Timing of Interrupt Exception-Handling Sequence ················································109 5.5 Interrupts During Operation of the Data Transfer Controller ············································109 5.6 Interrupt Response Time ····································································································112 Section 6 Data Transfer Controller 6.1 Overview ····························································································································113 6.1.1 Features ···················································································································113 6.1.2 Block Diagram ········································································································113 6.1.3 Register Configuration ····························································································114 6.2 Register Descriptions ·········································································································115 6.2.1 Data Transfer Mode Register (DTMR) ···································································115 6.2.2 Data Transfer Source Address Register (DTSR) ····················································116 6.2.3 Data Transfer Destination Register (DTDR) ·························································116 6.2.4 Data Transfer Count Register (DTCR) ···································································116 6.2.5 Data Transfer Enable Registers A to F (DTEA to DTEF) ······································117 6.3 Data Transfer Operation ·····································································································118 6.3.1 Data Transfer Cycle ································································································118 |
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