27-Bit, 2.5MHz to 42MHz

DC-Balanced LVDS Deserializers

Maxim Integrated

7

MAX9248/MAX9250

Pin Description

PIN

MAX9248

MAX9250

NAME

FUNCTION

11

R/F

Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_OUT

for latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low for a

falling latch edge. Internally pulled down to GND.

2

2

RNG1

LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel

clock input frequency. Internally pulled down to GND.

33

LVDS Supply Voltage. Bypass to LVDSGND with 0.1µF and 0.001µF capacitors in parallel as

close to the device as possible, with the smallest value capacitor closest to the supply pin.

4

4

IN+

Noninverting LVDS Serial-Data Input

5

5

IN-

Inverting LVDS Serial-Data Input

66

LVDSGND

LVDS Supply Ground

7

7

PLLGND

PLL Supply Ground

88

PLL Supply Voltage. Bypass to PLLGND with 0.1µF and 0.001µF capacitors in parallel as

close to the device as possible with the smallest value capacitor closest to the supply pin.

9

9

RNG0

LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel

clock input frequency. Internal pulldown to GND.

10

10

GND

Digital Supply Ground

11

11

Digital Supply Voltage. Supply for LVTTL/LVCMOS inputs and digital circuits. Bypass to

GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible with

the smallest value capacitor closest to the supply pin.

12

12

REFCLK

LVTTL/LVCMOS Reference Clock Input. Apply a reference clock that is within

±2% of the

serializer PCLK_IN frequency. Internally pulled down to GND.

13

13

PWRDWN

LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.

14

—

SS

LVTTL/LVCMOS Spread-Spectrum Input. SS selects the frequency spread of PCLK_OUT and

output data relative to PCLK_IN. Drive SS high for 4% spread and pull low for 2% spread.

15–23

15–23

CNTL_OUT0–

CNTL_OUT8

LVTTL/LVCMOS Control Data Outputs. CNTL_OUT[8:0] are latched into the next chip on the

rising or falling edge of PCLK_OUT as selected by R/F when DE_OUT is low, and are held

at the last state when DE_OUT is high.

24

24

DE_OUT

LVTTL/LVCMOS Data-Enable Output. High indicates RGB_OUT[17:0] are active. Low

indicates CNTL_OUT[8:0] are active.

25, 37

25, 37

Output Supply Ground

26, 38

26, 38

Output Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as

close to the device as possible with the smallest value capacitor closest to the supply pin.