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ISL8018EVAL3Z Datasheet(PDF) 3 Page - Intersil Corporation

Part # ISL8018EVAL3Z
Description  8A Low Quiescent Current High Efficiency Synchronous Buck Regulator
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL8018EVAL3Z Datasheet(HTML) 3 Page - Intersil Corporation

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ISL8018
3
FN7889.0
September 30, 2015
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Pin Descriptions
PIN
SYMBOL
DESCRIPTION
1, 19, 20
PGND
Power ground.
2, 3, 4
PHASE
Switching node connection. Connect to one terminal of the inductor.
5, 6, 7
VIN
Input supply voltage. Connect two 22µF ceramic capacitors to power ground.
8
PG
Power-good is an open-drain output. Use 10kΩ to 100kΩ pull-up resistor connected between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms from the output reaching regulation.
9
SYNCOUT
This pin outputs a 250µA current source that is turned on at the rising edge of the internal clock or
SYNCIN. When SYNCOUT voltage reaches 0.8V, a reset circuit will activate and discharge SYNCOUT to
0V. SYNCOUT is held at 0V in PFM light load to reduce quiescent current.
10
SYNCIN
Mode selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state if SYNCIN
is floating.
11
EN
Regulator enable pin. Enables the output when driven to high. Shuts down the chip and discharges the
output capacitor when driven to low.
12
FS
This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz
and configured for internal compensation if FS is connected to VIN.
13
VSET
VSET is the output margining setting of the regulators. Connect to SGND for -10%, keep it floating for
no margining and connect to VIN for +10%.
14
ISET
ISET is the peak output current limit and skip current limit setting of the regulators. Connect to SGND
for 3A, to VIN for 5A and keep it floating for 8A.
15
SS
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor
from SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
16, 17
COMP, VFB
The feedback network of the regulator, VFB, is the negative input to the transconductance error
amplifier. COMP is the output of the amplifier if the FS resistor is used. If internal compensation is used
(FS = VIN), the comp pin should be tied to SGND. The output voltage is set by an external resistor divider
connected to VFB. With a properly selected divider, the output voltage can be set to any voltage
between VIN and the 0.6V reference. While internal compensation offers a solution for many typical
applications, an external compensation network may offer improved performance for some designs.
In addition to regulation, VFB is also used to determine the state of PG.
18
SGND
Signal ground.
EPAD
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many
vias as possible under the pad connecting to the system GND plane for optimal thermal performance.


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