MAX7325AEG+ datasheet(10/17 Pages) MAXIM

Part #	MAX7325AEG+

Description	I2C Port Expander with 8 Push-Pull and 8 Open-Drain I/Os

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Manufacturer	MAXIM [Maxim Integrated Products]

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MAX7325

I2C Port Expander with 8 Push-Pull

and 8 Open-Drain I/Os

10

Maxim Integrated

Serial Interface

Serial Addressing

The MAX7325 operates as a slave that sends and

receives data through an I2C interface. The interface

uses a serial-data line (SDA) and a serial-clock line (SCL)

to achieve bidirectional communication between mas-

ter(s) and slave(s). The master initiates all data transfers

to and from the MAX7325 and generates the SCL clock

that synchronizes the data transfer (Figure 1).

SDA operates as both an input and an open-drain out-

put. A pullup resistor, typically 4.7k

Ω, is required on

SDA. SCL operates only as an input. A pullup resistor,

typically 4.7k

Ω, is required on SCL if there are multiple

masters on the 2-wire interface, or if the master in a sin-

gle-master system has an open-drain SCL output.

Each transmission consists of a START condition sent

by a master, followed by the MAX7325’s 7-bit slave

addresses plus R/W bits, 1 or more data bytes, and

finally a STOP condition (Figure 2).

START and STOP Conditions

Both SCL and SDA remain high when the interface is

not busy. A master signals the beginning of a transmis-

sion with a START (S) condition by transitioning SDA

from high to low while SCL is high. When the master

has finished communicating with the slave, the master

issues a STOP (P) condition by transitioning SDA from

low to high while SCL is high. The bus is then free for

another transmission (Figure 2).

Bit Transfer

One data bit is transferred during each clock pulse.

The data on SDA must remain stable while SCL is high

(Figure 3).

SCL

SDA

tR

tF

tBUF

START

CONDITION

STOP

CONDITION

REPEATED START CONDITION

START CONDITION

tSU,STO

tHD,STA

tSU,STA

tHD,DAT

tSU,DAT

tLOW

tHIGH

tHD,STA

Figure 1. 2-Wire Serial Interface Timing Details

SDA

SCL

START

CONDITION

STOP

CONDITION

SP

Figure 2. START and STOP Conditions

SDA

SCL

DATA LINE STABLE;

DATA VALID

CHANGE OF DATA

ALLOWED

Figure 3. Bit Transfer

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