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54F825SDM Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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54F825SDM Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 8 page  TLF9597 December 1994 54F74F825 8-Bit D-Type Flip-Flop General Description The ’F825 is an 8-bit buffered register It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems Also in- cluded in the ’F825 are multiple enables that allow multi- user control of the interface The ’F825 is functionally and pin compatible with AMD’s Am29825 Features Y TRI-STATE output Y Clock enable and clear Y Multiple output enables Y Direct replacement for AMD’s Am24825 Commercial Military Package Package Description Number 74F825SPC N24C 24-Lead (0300 Wide) Molded Dual-In-Line 54F825SDM (Note 2) J24F 24-Lead (0300 Wide) Ceramic Dual-In-Line 74F825SC (Note 1) M24B 24-Lead (0300 Wide) Molded Small Outline JEDEC 54F825FM (Note 2) W24C 24-Lead Cerpack 54F825LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier Type C Note 1 Devices also available in 13 reel Use suffix e SCX Note 2 Military grade device with environmental and burn-in processing Use suffix e SDMQB FMQB and LMQB Logic Symbols TLF9597 – 1 IEEEIEC TLF9597 – 4 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation RRD-B30M75Printed in U S A |
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