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DRV8305NQPHPRQ1 Datasheet(PDF) 9 Page - Texas Instruments |
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DRV8305NQPHPRQ1 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 54 page  9 DRV8305-Q1 www.ti.com SLVSD12A – MAY 2015 – REVISED MARCH 2016 Product Folder Links: DRV8305-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Electrical Characteristics (continued) PVDD = 4.4 to 45 V, DRV8305xQ: TJ = –40°C to 150°C, DRV8305xE: TJ = –40°C to 175°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IDRIVEN_LS Low-side peak sink current IDRIVEN_LS = 0000 0.02 A IDRIVEN_LS = 0001 0.03 IDRIVEN_LS = 0010 0.04 IDRIVEN_LS = 0011 0.05 IDRIVEN_LS = 0100 0.06 IDRIVEN_LS = 0101 0.07 IDRIVEN_LS = 0110 0.08 IDRIVEN_LS = 0111 0.25 IDRIVEN_LS = 1000 0.5 IDRIVEN_LS = 1001 0.75 IDRIVEN_LS = 1010 1 IDRIVEN_LS = 1011 1.25 IDRIVEN_LS = 1100, 1101, 1110, 1111 0.06 PASSIVE GATE PULL DOWN (GHx, GLx) RSLEEP_PD Gate pull down resistance, sleep mode EN_GATE = LOW; GHx to GND; 1000 Ω EN_GATE = LOW; GLx to GND; 500 Ω RSTANDBY_PD Gate pull down resistance, standby mode EN_GATE = LOW; GHx to GND; 1000 Ω EN_GATE = LOW; GLx to GND; 500 Ω ACTIVE GATE PULL DOWN (GHx, GLx) IHOLD Gate pull down current, holding EN_GATE = HIGH; GHx to SHx; GLx to SLx 50 mA ISTRONG Gate pull down current, strong EN_GATE = HIGH; GHx to SHx; GLx to SLx 1.25 A GATE TIMING tpd_lf-O Positive input falling to GHS_x falling PVDD = 12 V; CL = 1 nF; 50% to 50% 150 ns tpd_lr-O Positive input rising to GHS_x rising PVDD = 12 V; CL = 1 nF; 50% to 50% 150 ns td_min Minimum dead time after hand shaking 280 ns tdtp Dead time in addition to td_min DEAD_TIME = 000 35 ns DEAD_TIME = 001 52 DEAD_TIME = 010 88 DEAD_TIME = 011 440 DEAD_TIME = 100 880 DEAD_TIME = 101 1760 DEAD_TIME = 110 3520 DEAD_TIME = 111 5280 tPD_MATCH Propagation delay matching between high-side and low- side 50 ns tDT_MATCH Dead time matching 50 ns |
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