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DRV8305NEPHPQ1 Datasheet(PDF) 7 Page - Texas Instruments |
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DRV8305NEPHPQ1 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 54 page  7 DRV8305-Q1 www.ti.com SLVSD12A – MAY 2015 – REVISED MARCH 2016 Product Folder Links: DRV8305-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated 6.5 Electrical Characteristics PVDD = 4.4 to 45 V, DRV8305xQ: TJ = –40°C to 150°C, DRV8305xE: TJ = –40°C to 175°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (PVDD, DVDD, AVDD) VPVDD PVDD operating voltage 4.4 45 V Voltage regulator (VREG) operational 4.3 45 IPVDD_Operating PVDD operating supply current EN_GATE = HIGH; VREG no load; outputs HI-Z 20 mA IPVDD_Standby PVDD standby supply current EN_GATE = LOW; VREG no load 5 mA IPVDD_Sleep PVDD sleep supply current EN_GATE = LOW; Sleep Mode; TJ = –40 to 150 °C 60 200 μA EN_GATE = LOW; Sleep Mode; TJ = 150 to 175 °C 250 uA VAVDD Internal regulator voltage PVDD = 5.3 to 45 V 4.85 5 5.15 V PVDD = 4.4 to 5.3 V PVDD – 0.4 PVDD VDVDD Internal regulator voltage 3.3 V VOLTAGE REGULATOR (3.3-V or 5-V VREG) VVREG VREG DC output voltage PVDD = 5.4 to 45 V VREG × 0.97 VREG VREG × 1.03 V PVDD = 4.4 to 5.3 V; 5-V regulator PVDD – 0.4 PVDD PVDD = 4.4 to 5.3 V; 3.3-V regulator VREG × 0.97 VREG VREG × 1.03 VLineReg Line regulation ΔVOUT/ΔVIN 5.3 V ≤ VIN ≤ 12 V; IO = 1 mA 10 30 mV VLoadReg Load regulation ΔVOUT/ΔIOUT 100 μA ≤ IOUT ≤ 50 mA 30 mV Vdo Dropout voltage IOUT = 100 μA; 3.3 V 0.05 0.1 V IOUT = 50 mA; 3.3 V 0.2 0.4 LOGIC-LEVEL INPUTS (INHx, INLx, EN_GATE, SCLK, nSCS) VIL Input logic low voltage 0 0.8 V VIH Input logic high voltage 2 5 V RPD Internal pulldown resistor To GND 100 k Ω CONTROL OUTPUTS (nFAULT, SDO, PWRGD) VOL Output logic low voltage nFAULT; SDO; PWRGD; IO = 5 mA 0.5 V VOH Output logic high voltage SDO; IO = 5 mA VREG - 0.9 V IOH Output logic high leakage VO = 3.3 V –1 1 μA HIGH VOLTAGE TOLERANT LOGIC INPUT (WAKE) VIL_WAKE Output logic high voltage 1.1 1.41 V VIH_WAKE Output logic high leakage 1.42 1.75 V GATE DRIVE OUTPUT (GHx, GLx) VGHS High side gate driver Vgs voltage VPVDD = 8 to 45 V; IGATE < 30 mA 9 10 10.5 V VPVDD = 5.5 to 8 V; IGATE < 10 mA 7 10.5 VPVDD = 4.4 to 5.5 V; IGATE < 5 mA 5 9 VGLS Low-side gate driver Vgs voltage VPVDD = 8 to 45 V; IGATE < 30 mA 9 10 10.5 V VPVDD = 5.5 to 8 V; IGATE < 10 mA 9 10.5 VPVDD = 4.4 to 5.5 V; IGATE < 5 mA 8 10.5 PEAK CURRENT DRIVE TIMES (GHx, GLx) tDRIVE Peak sink or source current drive time TDRIVEP = 00; TDRIVEN = 00 220 ns TDRIVEP = 01; TDRIVEN = 01 440 TDRIVEP = 10; TDRIVEN = 10 880 TDRIVEP = 11; TDRIVEN = 11 1780 |
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