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DRV83053PHPR Datasheet(PDF) 5 Page - Texas Instruments |
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DRV83053PHPR Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 59 page  5 DRV8305 www.ti.com SLVSCX2B – AUGUST 2015 – REVISED FEBRUARY 2016 Product Folder Links: DRV8305 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) VCC is not a pin on the DRV8305, but a VCC supply voltage pullup is required for open-drain output nFAULT. External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CPVDD PVDD GND 4.7-µF ceramic capacitor rated for PVDD CAVDD AVDD GND 1-µF ceramic capacitor rated for 6.3 V CDVDD DVDD GND 1-µF ceramic capacitor rated for 6.3 V CVCPH VCPH PVDD 2.2-µF ceramic capacitor rated for 16 V CVCP_LSD VCP_LSD GND 1-µF ceramic capacitor rated for 16 V CCP1 CP1H CP1L 0.047-µF ceramic capacitor rated for PVDD CCP2 CP2H CP2L 0.047-µF ceramic capacitor rated for PVDD × 2 CVREG VREG GND 1-µF ceramic capacitor rated for 6.3 V RVDRAIN VDRAIN PVDD 100- Ω series resistor between VDRAIN and HS MOSFET DRAIN RnFAULT nFAULT VCC (1) 1-10 k Ω pulled up the MCU power supply RPWRGD PWRGD VCC (1) 1-10 k Ω pulled up the MCU power supply (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range referenced with respect to GND (unless otherwise noted) (1) MIN MAX UNIT Power supply voltage (PVDD) –0.3 45 V Power supply voltage ramp rate (VM) 0 2 V/µs Charge pump voltage (CP1H,CP1L, CP2L,CP2H, VCPH, VCP_LSD) –0.3 PVDD + 12 V High side gate driver voltage (GHA, GHB, GHC) –3 57 V Low-side gate driver voltage (GHA, GHB, GHC) –2 12 V High side gate driver source pin voltage (SHA, SHB, SHC) –5 45 V Low-side gate driver source pin voltage (SLA, SLB, SLC) –3 5 V Internal phase clamp pin voltage difference {(GHA-SHA), (GHB-SHB), (GHC-SHC), (GLA-SLA), (GLB-SLB), (GLC-SLC)} –0.3 15 V Drain pin voltage drain (VDRAIN) –0.3 45 V Max source current (VDRAIN) – limit current with external series resistor –20 mA Max sink current (VDRAIN) 2 mA Voltage difference between supply and VDRAIN (PVDD-VDRAIN) –10 10 V Control pin voltage range (INHA, INLA, INHB, INLB, INHC, INLC, EN_GATE, SCLK, SDI, SCS, SDO, nFAULT, PWRGD) –0.3 5.5 V Open drain pins skink current (nFAULT, PWRGD) 7 mA Wake pin voltage (WAKE) –0.3 45 V Wake pin sink current (WAKE) – limit with external series resistor 1 mA Sense amp voltage (SPA, SNA, SPB, SNB, SPC, SNC) –2 5 V Externally applied reference voltage (VREG) – when vreg_vref = 1 –0.3 5.5 V Externally applied reference sink current (VREG) – when vreg_vref = 1 100 µA Operating ambient temperature, TA –40 125 °C Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –55 150 °C |
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