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DRV8305-Q1 Datasheet(PDF) 10 Page - Texas Instruments |
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DRV8305-Q1 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 54 page 10 DRV8305-Q1 SLVSD12A – MAY 2015 – REVISED MARCH 2016 www.ti.com Product Folder Links: DRV8305-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Electrical Characteristics (continued) PVDD = 4.4 to 45 V, DRV8305xQ: TJ = –40°C to 150°C, DRV8305xE: TJ = –40°C to 175°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT SHUNT AMPLIFIER GCSA Current sense amplifier gain GAIN_CSx = 00 10 V/V GAIN_CSx = 01 19.9 GAIN_CSx = 10 39.8 GAIN_CSx = 11 79.5 GERR Current sense amplifier gain error Input differential > 0.025 V; TJ = –40 to 150 °C –3% 3% Input differential > 0.025 V; TJ = 150 to 175 °C –4% 4% tSETTLING Current sense amplifier settling time Settling time to 1%; no blanking; GCSA = 10; Vstep = 0.46 V 300 ns Settling time to 1%; no blanking; GCSA = 20; Vstep = 0.46 V 600 Settling time to 1%; no blanking; GCSA = 40; Vstep = 0.46 V 1.2 µs Settling time to 1%; no blanking; GCSA = 80; Vstep = 0.46 V 2.4 VIOS DC input offset GCSA = 10; input shorted; RTI –4 4 mV VVREF_ERR Reference buffer error (DC) Internal or external VREF; TJ = –40 to 150 °C –2% 2% Internal or external VREF; TJ = 150 to 175 °C –3% 3% VDRIFTOS Input offset error drift GCSA = 10; input shorted; RTI 10 µV/C IBIAS Input bias current VIN_COM = 0; SOx open 100 µA IOFFSET Input bias current offset IBIAS (SNx-SPx); VIN_COM = 0; SOx open 1 µA VIN_COM Common input mode range –0.15 0.15 V VIN_DIFF Differential input range -0.48 0.48 V CMRR Common mode rejection ration External input resistance matched; DC; GCSA = 10 60 80 dB External input resistance matched; 20 kHz; GCSA = 10 60 80 PSRR Power supply rejection ratio DC (<120 Hz); GCSA = 10 150 dB 20 kHz; GCSA = 10 90 VSWING Output voltage swing PVDD > 5.3 V 0.3 4.7 V VSLEW Output slew rate GCSA = 10; RL = 0 Ω; CL = 60 pF 5.2 10 V/µs IVO Output short circuit current SOx shorted to ground 20 mA UGB Unity gain bandwidth product GCSA = 10 2 MHz VOLTAGE PROTECTION VAVDD_UVLO AVDD under voltage Fault Relative to GND 3.3 3.5 V VVREG_UV VREG under voltage Fault VREG_UV_LEVEL = 00 VREG x 0.9 V VREG_UV_LEVEL = 01 VREG x 0.8 VREG_UV_LEVEL = 10 VREG x 0.7 VREG_UV_LEVEL = 11 VREG x 0.7 VVREG_UV_DGL VREG under voltage monitor deglitch time 1.5 2 µs VPVDD_UVFL Under voltage protection warning, PVDD PVDD falling 7.7 8.1 V PVDD rising 7.9 8.3 |
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Similar Description - DRV8305-Q1_16 |
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