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RM48L950DPGET Datasheet(PDF) 11 Page - Texas Instruments |
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RM48L950DPGET Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 179 page  RM48L950, RM48L750, RM48L550 www.ti.com SPNS174C – APRIL 2012 – REVISED JUNE 2015 4.3 Terminal Functions Section 4.3.1 and Section 4.3.2 identify the external signal names, the associated pin or ball numbers along with the mechanical package designator, the pin or ball type (Input, Output, I/O, Power, or Ground), whether the pin or ball has any internal pullup or pulldown, whether the pin or ball can be configured as a GPIO, and a functional pin or ball description. The first signal name listed is the primary function for that terminal. The signal name in bold is the function being described. For information on how to select between different multiplexed functions, see the RM48x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (SPNU503) . NOTE In the Terminal Functions table below, the "Reset Pull State" is the state of the pull applied to the terminal while nPORRST is low and immediately after nPORRST goes High. The default pull direction may change when software configures the pin for an alternate function. The "Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given terminal by the IOMM control registers. All I/O signals except nRST are configured as inputs while nPORRST is low and immediately after nPORRST goes High. While nPORRST is low, the input buffers are disabled, and the output buffers are disabled with the default pulls enabled. All output-only signals have the output buffer disabled and the default pull enabled while nPORRST is low, and are configured as outputs with the pulls disabled immediately after nPORRST goes High. 4.3.1 PGE Package 4.3.1.1 Multibuffered Analog-to-Digital Converters (MibADCs) Table 4-1. PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2) TERMINAL RESET SIGNAL PULL PULL TYPE DESCRIPTION 144 TYPE SIGNAL NAME STATE PGE ADREFHI(1) 66 Input ADC high reference supply ADREFLO(1) 67 Input ADC low reference supply N/A None VCCAD(1) 69 Power Operating supply for ADC VSSAD(1) 68 Ground AD1EVT/MII_RX_ER/RMII_RX_ER 86 I/O Pulldown Programmable, 20 µA ADC1 event trigger input, or GPIO MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 I/O Pullup Programmable, 20 µA ADC2 event trigger input, or GPIO AD1IN[0] 60 AD1IN[1] 71 AD1IN[2] 73 AD1IN[3] 74 Input N/A None ADC1 analog input AD1IN[4] 76 AD1IN[5] 78 AD1IN[6] 80 AD1IN[7] 61 (1) The ADREFHI, ADREFLO, VCCAD, and VSSAD connections are common for both ADC cores. Copyright © 2012–2015, Texas Instruments Incorporated Terminal Configuration and Functions 11 Submit Documentation Feedback |
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