Connection Diagrams

Pin Assignment for

DIP SOIC and Flatpak

TLF9511 – 1

Pin Assignment

for LCC

TLF9511 – 2

Unit LoadingFan Out

54F74F

Pin Names

Description

UL

HIGHLOW

Data Inputs

1010

MR

Master Reset (Active LOW)

1010

CP

Clock Pulse Input (Active Rising Edge)

1010

Data Outputs

50333

b

1 mA20 mA

Mode Select-Function Table

Operating Mode

Inputs

Output

MR

CP

Reset (Clear)

L

X

X

L

Load ‘1’

H

L

hH

Load ‘0’

H

L

lL

transition

transition

Logic Diagram

TLF9511 – 4

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays

2