VX6953CB datasheet(7/107 Pages) STMICROELECTRONICS

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VX6953CB Datasheet(PDF) 7 Page - STMicroelectronics

Part #	VX6953CB

Description	5.1 megapixel EDOF camera module

Download	107 Pages

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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7 / 107 page

8209023 Rev 5

7/107

VX6953CB

List of tables

Table 1.

Technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2.

Reference documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3.

Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4.

Power management matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5.

Power-up sequence timing constraints for CCP2/CSI2 communications . . . . . . . . . . . . . . 20

Table 6.

Power-down sequence timing constraints for CSI2 communications . . . . . . . . . . . . . . . . . 23

Table 7.

POR cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 8.

System input clock frequency range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 9.

Status registers [0x0000 to 0x000F] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 10.

Frame format description registers [0x0040 to 0x007F] . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 11.

Analog gain description [0x0080 to 0x0093]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 12.

Data format description registers [0x00C0 to 0x00FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 13.

Setup registers [0x0100 to 0x01FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 14.

Integration time and gain registers [0x0200 to 0x02FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 15.

Video timing registers [0x0300 to 0x03FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 16.

Image scaling registers [0x0400 to 0x04FF]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 17.

Image compression registers [0x0500 to 0x05FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 18.

Test pattern registers [0x0600 to 0x06FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 19.

Fifo water mark registers [0x0700 to 0x0701]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 20.

DPHY registers [0x0810 to 0x0811] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 21.

Binning registers [0x0900 to 0x0902] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 22.

Shading correction registers [0x0B00] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 23.

Defect correction registers [0x0B05 to 0x0B09] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 24.

EDOF registers [0x0B80 to 0x0B8A] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 25.

Color feedback registers [0x0B8C to 0x0B95] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 26.

Integration time and gain parameter limit registers [0x1000 to 0x10FF]. . . . . . . . . . . . . . . 41

Table 27.

Video timing parameter limit registers [0x1100 to 0x11FF]. . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 28.

Image scaling parameter limit registers [0x1200 to 0x120B] . . . . . . . . . . . . . . . . . . . . . . . 46

Table 29.

Image compression parameter limit registers [0x1300 to 0x13FF] . . . . . . . . . . . . . . . . . . . 46

Table 30.

CSI lane mode capability registers [0x1600 - 0x1602] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 31.

Binning capability registers [0x1700 to 0x170B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 32.

Manufacturer specific registers [0x31E8 to 0x31EB] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 33.

Binning register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 34.

External clock frequency examples - 5.0 Mpixel RAW10 14.5 fps (CSI-2) . . . . . . . . . . . . . 58

Table 35.

External clock frequency examples - 5.0 Mpixel RAW10 15 fps (CSI-2) . . . . . . . . . . . . . . 58

Table 36.

External clock frequency examples - 5.0 Mpixel 10-8 compressed 15 fps . . . . . . . . . . . . . 59

Table 37.

Example - 5.0 Mpixel 10-8 compressed 16.65 fps (CSI-2) . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 38.

External clock frequency examples - 1080x1920 in 10-8 bit @ 30fps (CCP) . . . . . . . . . . . 59

Table 39.

720x1280 @ 30 fps in RAW10 (CSI2/CCP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 40.

Analog gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 41.

EDOF registers [0x0B80 to 0x0B8A] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 42.

Color feedback registers [0x0B8C to 0x0B95] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 43.

Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 44.

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 45.

Power supplies VDIG, VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 46.

In-rush current VDIG, VANA for CCP2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 47.

In-rush current VDIG, VANA for CSI-2 interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 48.

Ripple requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

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