SN74LV4046APWRG4 datasheet(5/26 Pages) TI1

Part #	SN74LV4046APWRG4

Description	High-Speed CMOS Logic Phase-Locked Loop

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SN74LV4046A

www.ti.com

SCES656D – FEBRUARY 2006 – REVISED SEPTEMBER 2015

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

TEST CONDITIONS

PARAMETER

VCC (V)

MIN

TYP

MAX

UNIT

VI (V)

IO (mA)

VCO

3 to 3.6

VCC × 0.7

VIH

High-level input voltage

INH

V

4.5 to 5.5

VCC × 0.7

3 to 5.5

VCC × 0.3

VIL

Low-level input voltage

INH

V

4.5 to 5.5

VCC × 0.3

3 to 3.6

VCC – 0.1

CMOS

–0.05

High-level

VOH

VCOOUT

VIL or VIH

4.5 to 5.5

VCC – 0.1

V

output voltage

TTL

–12

4.5 to 5.5

3.8

3 to 3.6

0.1

CMOS

0.05

VCOOUT

4.5 to 5.5

0.1

Low-level

VOL

VIL or VIH

V

TTL

12

4.5 to 5.5

0.55

output voltage

C1A, C1B

12

4.5 to 5.5

0.65

(test purposes only)

II

Input leakage current

INH, VCOIN

VCC or GND

5.5

±1

μA

R1 range(1)

3 to 5.5

3

50

k

Ω

R2 range(1)

3 to 5.5

3

50

k

Ω

3 to 3.6

40

No Limit

C1 capacitance range

pF

4.5 to 5.5

40

No Limit

3 to 3.6

1.1

1.9

Over the range specified for

Operating voltage range

VCOIN

V

R1 for linearity(2)

4.5 to 5.5

1.1

3.2

PHASE COMPARATOR

3 to 3.6

VCC × 0.7

DC-coupled high-level

SIGIN,

VIH

input voltage

COMPIN

4.5 to 5.5

VCC × 0.7

3 to 3.6

VCC × 0.3

SIGIN,

VIL

DC-coupled low-level input voltage

V

COMPIN

4.5 to 5.5

VCC × 0.3

–0.05

3 to 5.5

VCC – 0.1

CMOS

High-level

PCPOUT,

VOH

VIL or VIH

–6

3 to 3.6

2.48

V

output voltage

PCNOUT

TTL

–12

4.5 to 5.5

3.8

3 to 3.6

0.1

0.02

CMOS

Low-level

PCPOUT,

4.5 to 5.5

0.1

VOL

VIL or VIH

V

output voltage

PCNOUT

4

4.5 to 5.5

0.4

TTL

3 to 3.6

±11

SIGIN,

II

Input leakage current

VCC or GND

μA

COMPIN

4.5 to 5.5

±29

IOZ

3-state off-state current

PC2OUT

VIL or VIH

3 to 5.5

±5

μA

3

800

SIGIN,

VI at self-bias operating

RI

Input resistance

k

Ω

COMPIN

point, VI = 0.5 V

4.5

250

DEMODULATOR

RS > 300 kΩ, Leakage

3 to 3.6

50

300

RS

Resistor range

current can influence

k

Ω

4.5 to 5.5

50

300

VDEMOUT

3 to 3.6

±30

VI = VVCOIN = VCC/2, Values

VOFF

Offset voltage VCOIN to VDEM

mV

taken over RS range

4.5 to 5.5

±20

Pins 3, 5, and 14 at VCC,

ICC

Quiescent device current

Pin 9 at GND, II at pins 3

5.5

50

μA

and 14 to be excluded

(1)

The value for R1 and R2 in parallel should exceed 2.7 k

Ω.

(2)

The maximum operating voltage can be as high as VCC – 0.9 V; however, this may result in an increased offset voltage.

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