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ICE1PCS01G Datasheet(PDF) 9 Page - Infineon Technologies AG |
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ICE1PCS01G Datasheet(HTML) 9 Page - Infineon Technologies AG |
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9 / 18 page  CCM-PFC ICE1PCS01/G Functional Description Preliminary Data Preliminary Datasheet 9 28 May 2003 Figure 9 Peak Current Limit (PCL) 3.4.4 Open Loop Protection / Input Under Voltage Protect (OLP) Whenever VSENSE voltage falls below 0.8V, or equivalently VOUT falls below 16% of its rated value, it indicates an open loop condition (i.e. VSENSE pin not connected) or an insufficient input voltage VIN for normal operation. In this case, most of the blocks within the IC will be shutdown. It is implemented using comparator C3 with a threshold of 0.8V as shown in the IC block diagram in Figure 2. 3.4.5 Output Under Voltage Detection (OUV) In the event of main interrupt or brown-out condition, the PFC system is not able to deliver the rated output power. This will cause the output voltage VOUT to drop below its rated value. The IC provides an output under voltage detection that checks if VOUT is falling below 50% of its rated value. Comparator C4 as shown in the device block diagram (Figure 2) senses the voltage at pin 6 (VSENSE) with a reference of 2.5V. If comparator C4 trips, the IC will be shut down as in OLP. The IC will be ready to restart if there is sufficient VIN to pull VOUT out of OLP. 3.4.6 Over-Voltage Protection (OVP) Whenever VOUT exceeds the rated value by 5%, the over-voltage protection OVP is active as shown in Figure 7. This is implemented by sensing the voltage at pin VSENSE with respect to a reference voltage of 5.25V. A VSENSE voltage higher than 5.25V will immediately reduce the output duty cycle, bypassing the normal voltage loop control. This results in a lower input power to reduce the output voltage VOUT. 3.5 Frequency Setting The switching frequency of the PFC converter can be set with an external resistor R5 at FREQ pin. The pin voltage VFREQ is typically 2.5V. The corresponding capacitor for the oscillator is integrated in the device and the R5/frequency relationship is given at the “Electrical Characteristic” section. The recommended operating frequency range is from 50kHz to 250kHz. As an example, a R5 of 33k Ω at pin FREQ will set a switching frequency FSW of 133kHz typically. 3.6 Average Current Control 3.6.1 Complete Current Loop The complete system current loop is shown in Figure 10. Figure 10 Complete System Current Loop It consists of the current loop block which averages the voltage at pin ISENSE, resulted from the inductor current flowing across R1. The averaged waveform is compared with an internal ramp in the ramp generator and PWM block. Once the ramp crosses the average waveform, the comparator C1 turns on the driver stage through the PWM logic block. The Nonlinear Gain block defines the amplitude of the inductor current. The following sections describe the functionality of each individual blocks. 3.6.2 Current Loop Compensation The compensation of the current loop is done at the ICOMP pin. This is the OTA2 output and a capacitor C3 has to be installed at this node to ground (see Figure 10). Under normal mode of operation, this pin gives a voltage which is proportional to the averaged inductor current. This pin is internally shorted to 5V in the event of IC shuts down when OLP and UVLO occur. 3.6.3 Pulse Width Modulation (PWM) The IC employs an average current control scheme in continuous conduction mode (CCM) to achieve the power factor correction. ISENSE ICE1PCS01/G R1 R2 I INDUCTOR OP1 1.43x Current Limit 300ns C2 Deglitcher Turn Off Driver 1.5V Full-wave Rectifier R S ICE1PCS01/G Vout L1 C2 R3 R4 Gate Driver D1 From Full-wave Retifier GATE R1 R2 OTA2 ICOMP 4V Current Loop Compensation Current Loop Nonlinear Gain 1.1mS +/-50uA (linear range) C3 S2 Fault ISENSE C1 PWM Comparator PWM Logic Q Input From Voltage Loop voltage proportional to averaged Inductor current R7 |
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