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HYB39S256400DCL-6 Datasheet(PDF) 11 Page - Infineon Technologies AG |
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HYB39S256400DCL-6 Datasheet(HTML) 11 Page - Infineon Technologies AG |
11 / 28 page HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM Pin Configuration Data Sheet 11 Rev. 1.02, 2004-02 10072003-13LE-FGQQ 2.4 Block Diagrams Figure 2 Block Diagram for 64M x 4 SDRAM (13/11/2 addressing) Me m o r y A rra y Ba n k 1 81 9 2 x2 0 4 8 x4 B it Me mo r y A rra y Ba n k 2 81 9 2 x 2 048 x4 B it Me m o r y Arra y Ba n k 3 81 9 2 x2 0 4 8 x4 B it S P B 041 27 _ 2 Co lu m n A d d re s s Co u n te r Ro w De c o d e r Me m o r y A rray Ba n k 0 81 96 x2 0 4 8 x4 B it Ro w De c o d e r Ro w De c o d e r Ro w De c o d e r Ro w A d d re s s Bu ffe r C o lu m n A ddre s s Bu ffe r R e fres h C o u nte r A0 - A 1 2 , BA 0 , B A 1 A0 - A 9 , A1 1 , AP, BA 0 , B A 1 C o lu m n A d d re s s e s R ow A d d res s e s In p u t B u ffe r O u tp u t B u ffe r DQ0 - D Q 3 C o ntro l L og ic & Tim in g G e n e ra to r |
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