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HYS64T64020GDL Datasheet(PDF) 8 Page - Infineon Technologies AG |
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HYS64T64020GDL Datasheet(HTML) 8 Page - Infineon Technologies AG |
8 / 48 page HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A 512 Mbit DDR2 SDRAM Overview Data Sheet 8 Rev. 0.91, 2004-06 09122003-FTXN-KM26 1.3 Pin Configuration The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 5 (200 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1 Table 4 Components on Modules 1) 1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet. Product Type DRAM Components DRAM Density DRAM Organisation HYS64T32000GDL HYB18T512160AC 512 Mbit 32M ×16 HYS64T64020GDL HYS64T32000HDL 2) HYB18T512160AF 2) 2) Green Product 512 Mbit 32M ×16 HYS64T64020HDL 2) HYS64T128021GDL HYB18T512800AC 512 Mbit 64M ×8 HYS64T128021HDL 2) HYB18T512800AF 2) 512 Mbit 64M ×8 Table 5 Pin Configuration of SO-DIMM Pin# Name Pin Type Buffer Type Function Clock Signals 30 CK0 I SSTL Clock Signals 2:0 164 CK1 I SSTL 32 CK0 ISSTL Complement Clock Signals 2:0 166 CK1 ISSTL 79 CKE0 I SSTL Clock Enable Rank 0 80 CKE1 I SSTL Clock Enable Rank 1 Note: 2-rank module NC NC — Note: 1-rank module Control Signals 110 S0 ISSTL Chip Select Rank 0 115 S1 ISSTL Chip Select Rank 1 Note: 2-rank module NC NC — Note: 1-rank module 108 RAS ISSTL Row Address Strobe 113 CAS ISSTL Column Address Strobe 109 WE ISSTL Write Enable Address Signals 107 BA0 I SSTL Bank Address Bus 1:0 106 BA1 I SSTL 102 A0 I SSTL Address Bus 4:0 101 A1 I SSTL 100 A2 I SSTL 99 A3 I SSTL 98 A4 I SSTL |
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