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HYS64D32020GDL Datasheet(PDF) 8 Page - Infineon Technologies AG |
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HYS64D32020GDL Datasheet(HTML) 8 Page - Infineon Technologies AG |
8 / 31 page HYS64D[1600x/32020]GDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules Pin Configuration Data Sheet 8 V1.2, 2003-08 2 Pin Configuration Table 3 Pin Definitions and Functions Symbol Type 1) 1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not Connected; NU: Not Usable Function A0 - A12 I Address Inputs BA0, BA1 I Bank Address DQ0 - DQ63 I/O Data Input/Output RAS, CAS, WE I Command Input CKE0 - CKE1 I Clock Enable DQS0 - DQS7 I/O SDRAM Data Strobe CK0 - CK1, I SDRAM Clock (true signal) CK0 - CK1 I SDRAM Clock (complementary signal) DM0 - DM8 I Data Mask S0, S1 2) 2) CKE1 and S1 are used on two bank modules only IChip Select V DD PWR Power (+ 2.5 V) V SS GND Ground V DDQ PWR I/O Driver power supply VDDID PWR VDD Indentification flag V REF AI I/O reference supply V DDSPD PWR Serial EEPROM power supply SCL I Serial bus clock SDA I/O Serial bus data line SA0 - SA2 I slave address select NC NC Not Connected NU NU Not Usable, reserved for future use Table 4 Address Format Density Organization Memory Ranks SDRAMs # of SDRAMs # of row/bank/ columns bits Refresh Period Interval 128MB 16M × 64 1 16M × 16 4 13/2/9 8K 64 ms 7.8 µs 256MB 32M × 64 2 16M × 16 8 13/2/9 8K 64 ms 7.8 µs |
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