HYR16xx40G / HYR18xx40G

Rambus RIMM Modules

INFINEON Technologies

10

7.01

1) Table below lists parameters and specifications for different storage capacity RIMM Modules that use 288 Mbit

RDRAM devices.

2) Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM, CTMN,

.....CFM and CFMN).

3.) If the RIMM module meets the folowwing specifications, then it is compliant to the specification. If the RIMM

.....module does not meet these specifications, then the specification can be adjusted by the “Adjusted

∆T

.....Specification” table.

Adjusted

∆T

a) Where:

N = Nuber of RDRAM devices installed on the RIMm module

DZ0 = delta Z0% =(max Z0 - minZ0)/(min Z0)

AC Electrical Specifications

Symbol

Parameter and Conditions

Limit Values

Unit

min.

typ.

max.

Z

Module Impedance

25.2

28

30.8

Ω

T

PD

Average clock delay from finger of all RSL clock

nets (CTM, CTMN, CFM and CFMN)

––

See

Table

1)

ns

PD

Propagation delay variation of RSL signals with

respect to T

PD

– 21

–

21

ps

Propagation delay variation of RSL signals with

respect to T

PD

– 24

–

24

ps

PD-CMOS

Propagation delay variation of SCK and CMD

signals with respect to an average clock delay

2)

– 100

–

100

ps

V

Attenuation Limit

––

See

Table

1)

%

V

Forward crosstalk coefficient

(300 ps input rise time @ 20%-80%)

––

See

Table

1)

%

V

Backward crosstalk coefficient

(300 ps input rise time @ 20%-80%)

––

See

Table

1)

%

Symbol

Parameter and Conditions

Adjusted Min/Max

Absolute

Min /Max

Unit

∆T

PD

Propagation delay variation of RSL signals

with respect to T

+/-[17+(18*N*

-30

30

ps

Propagation delay variation of RSL signals

with respect to T

+/-[24+(18*N*

∆Z0)]

-50

50

ps