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HYB39S128400CT-7.5 Datasheet(PDF) 8 Page - Infineon Technologies AG

Part # HYB39S128400CT-7.5
Description  128-MBit Synchronous DRAM
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

HYB39S128400CT-7.5 Datasheet(HTML) 8 Page - Infineon Technologies AG

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HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies
8
9.01
DQM
LDQM
UDQM
Input
Pulse
Active
High
The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.
One DQM input is present in x4 and x8 SDRAMs, LDQM
and UDQM controls the lower and upper bytes in x16
SDRAMs.
V
DD
V
SS
Supply ––
Power and ground for the input buffers and the core logic.
V
DDQ
V
SSQ
Supply ––
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
Signal Pin Description (cont’d)
Pin
Type
Signal Polarity Function


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