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HYB39S256400DT-6 Datasheet(PDF) 10 Page - Infineon Technologies AG |
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HYB39S256400DT-6 Datasheet(HTML) 10 Page - Infineon Technologies AG |
10 / 22 page INFINEON Technologies 10 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Operation Definition All of SDRAM operations are defined by states of control signals CS,RAS,CAS,WE,and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands. Operation Device State CKE n-1 CKE n DQM BA0 BA1 AP= A10 Addr . CS RAS CAS WE Bank Active Idle3 H X XV VV L L H H Bank Precharge Any H X X V L X L L H L Precharge All Any H X X X H X L L H L Write Active3 HX X V L V L H L L Write with Autoprecharge Active3 H X XVH V L H L L Read Active3 H X X V L V LH LH Read with Autoprecharge Active3 H X XVH V L H L H Mode Register Set Idle H X X V V V L L L L No Operation Any H X X X X X L H H H Burst Stop Active H XX XX X L H H L Device Deselect Any H XX XX X H XX X Auto Refresh Idle H H X X X X L L L H Self Refresh Entry Idle H L X X X X L L L H Self Refresh Exit Idle (Self Refr.) L H XX XX HX X X L HHX Clock Suspend Entry Active H L X X X X X X X X Power Down Entry (Precharge or active standby) Idle H L XX XX HX X X Active4 LH H H Clock Suspend Exit Active L H XX XX XX XX Power Down Exit Any (Power Down) L H XX XX HX X X LH H L Data Write/Output Enable Active H X L X X X X X X X Data Write/Output Disable Active H X H X X X X X X X Notes 1. V = Valid, x = Don’t Care, L = Low Level, H = High Level 2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3. This is the state of the banks designated by BA0, BA1 signals. 4. Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle device is in clock suspend mode. |
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