HYB25D512800BC-6 datasheet(9/90 Pages) INFINEON

Part #	HYB25D512800BC-6

Description	512Mbit Double Data Rate SDRAM

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Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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9 / 90 page

Data Sheet

9

Rev. 1.2, 2004-06

512Mbit Double Data Rate SDRAM

DDR SDRAM

HYB25D512[40/80/16]0B[C/T]

HYB25D512[40/80/16]0B[E/F]

1Overview

1.1

Features

•

Double data rate architecture: two data transfers per clock cycle

•

Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the

receiver

•

DQS is edge-aligned with data for reads and is center-aligned with data for writes

•

Differential clock inputs (CK and CK)

•

Four internal banks for concurrent operation

•

Data mask (DM) for write data

•

DLL aligns DQ and DQS transitions with CK transitions

•

Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS

•

Burst Lengths: 2, 4, or 8

•

CAS Latency: (1.5), 2, 2.5, 3

•

Auto Pre charge option for each burst access

•

Auto Refresh and Self Refresh Modes

•7.8

µs Maximum Average Periodic Refresh Interval

•

2.5 V (SSTL_2 compatible) I/O

•

V

DDQ = 2.5 V ± 0.2 V and 2.6 V ± 0.1 V for DDR400

•

V

DD = 2.5 V ± 0.2 V and 2.6 V ± 0.1 V for DDR400

•

P-TFBGA-60 and P-TSOPII-66 package

Table 1

Performance

Product Type Speed Code

-5

-6

-7

Unit

Speed Grade

DDR400B

DDR333B

DDR266A

–

max. Clock Frequency

@CL3

f

CK3

200

166

143

MHz

@CL2.5

f

CK2.5

166

143

MHz

@CL2

f

CK2

133

MHz

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