TUSB8041-Q1

SLLSEE6B – JULY 2014 – REVISED JANUARY 2016

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7.4 Thermal Information

TUSB8041-Q1

PAP

UNIT

64 PINS

26.2

11.5

10.4

°C/W

0.2

10.3

0.6

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

(6)

The junction-to-board characterization parameter,

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

7.5 Electrical Characteristics, 3.3-V I/O

over operating free-air temperature range (unless otherwise noted)

PARAMETER

OPERATION

TEST CONDITIONS

MIN

MAX

UNIT

VDD33

2

VDD33

V

0

0.8

VDD33

V

JTAG pins only

0

0.55

Input voltage

0

VDD33

V

0

VDD33

V

0

25

ns

0.13 x VDD33

V

High-level output voltage

VDD33

2.4

V

Low-level output voltage

VDD33

0.4

V

VDD33

±20

µA

High-impedance, output current with

internal pullup or pulldown

VDD33

±250

µA

VDD33

±15

µA

(1)

Applies to external inputs and bidirectional buffers.

(2)

Applies to external outputs and bidirectional buffers.

(3)

Applies to GRSTz.

(4)

Applies to pins with internal pullups/pulldowns.

(5)

Applies to external input buffers.

10

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