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HYB18T1G160AFL-37 Datasheet(PDF) 11 Page - Infineon Technologies AG |
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HYB18T1G160AFL-37 Datasheet(HTML) 11 Page - Infineon Technologies AG |
11 / 89 page HYB18T1G400/800/160AF 1Gb DDR2 SDRAM INFINEON Technologies Page 11 Rev. 1.02 May 2004 Block Diagram 32Mbit x 8 I/O x 4 Internal Memory Banks (64Mb x 8 Organisation with 14 Row, 3 Bank and 11 Column External Addresses) RAS CAS CK CS WE CK Column-Address Counter/Latch Mode 10 A0-A13, BA0-BA2 CKE 17 I/O Gating DM Mask Logic Bank0 Memory Array (16384 x256x32) Sense Amplifiers Bank0 Bank1 Bank7 17 8 2 2 2 32 COL0,1 DQ0-DQ7, DM DQS Column Decoder 256 (x32) Registers 16384 17 1 DQS CK, CK DLL 8 8 8 Input Register 1 1 1 1 1 32 4 32 Data Mask Data CK, COL0,1 COL0,1 DQS Generator 1 1 8 32 Write FIFO & Drivers CK 8 8 DQS 1 1 8 8 8 8 8 8 8 8 DQS AP 17 8 8 Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi- rectional DQ and DQS signals. |
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