 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
HYB25D512160AT-6 Datasheet(PDF) 6 Page - Infineon Technologies AG |
|
||||||||||||||||||||||||||||||
HYB25D512160AT-6 Datasheet(HTML) 6 Page - Infineon Technologies AG |
|
|
6 / 76 page  HYB25D512[16/40/80]0AT–[6/7/7F] Overview Data Sheet 6 Rev. 1.0, 2004-03 1 Overview 1.1 Features • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is center-aligned with data for writes • Differential clock inputs (CK and CK) • Four internal banks for concurrent operation • Data mask (DM) for write data • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst Lengths: 2, 4, or 8 • CAS Latency: (1.5), 2, 2.5, 3 • Auto Precharge option for each burst access • Auto Refresh and Self Refresh Modes •7.8 µs Maximum Average Periodic Refresh Interval • 2.5 V (SSTL_2 compatible) I/O • V DDQ = 2.5 V ± 0.2 V (DDR266A, DDR333) • V DD = 2.5 V ± 0.2 V (DDR266, DDR333) • P-TSOP66II-1 package 1.2 Description The 512Mbit Double Data Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. The 512Mbit Double Data Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512Mbit Double Data Rate SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for Writes. The 512Mbit Double Data Rate SDRAM operates from a differential clock (CK and CK; the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration Table 1 Performance –6/–7/–7F Part Number Speed Code –6–7 -7F Unit Speed Grade Component DDR333B DDR266A DDR266 — Module PC2700–2533 PC2100-2033 PC2100-2022 — max. Clock Frequency @CL3 f CK3 166 — — MHz @CL2.5 f CK2.5 166 143 143 MHz @CL2 f CK2 133 133 133 MHz |
Similar Part No. - HYB25D512160AT-6 |
|
Similar Description - HYB25D512160AT-6 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
