HYB25D256[800/160]BT(L)-[5/5A]

256MBit Double Data Rata SDRAM

Page 6 of 29

2003-01-10, V0.9

Block Diagram (16Mb x 16)

1

DQS

CK, CK

DLL

RAS

CAS

CK

CS

WE

CK

Column-Address

Counter/Latch

Mode

9

A0-A11,

BA0, BA1

CKE

15

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(8192 x 256x 32)

Sense Amplifiers

Bank1

Bank2

Bank3

13

8

1

2

2

16

16

16

Input

Register

1

1

1

1

1

32

32

2

32

clk

out

Data

Mask

Data

CK,

COL0

COL0

COL0

clk

in

DQS

Generator

16

16

16

16

16

32

DQ0-DQ15,

DM

LDQS, UDQS

2

Write

FIFO

&

Drivers

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of

the device; it does not represent an actual circuit implementation.

Note: UDM and LDM are unidirectional signals (input only), but is internally loaded to match the

load of the bidirectional DQ , UDQS and LDQS signals.

Column

Decoder

256

(x32)

Registers

8192

13

CK