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HYB18T256800AF-3 Datasheet(PDF) 3 Page - Infineon Technologies AG |
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HYB18T256800AF-3 Datasheet(HTML) 3 Page - Infineon Technologies AG |
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3 / 90 page  HYB18T256400/800/160AF 256Mb DDR2 SDRAM INFINEON Technologies Page 3 Rev. 1.02 May 2004 Rainer.Weidlich@Infineon.com Features • High Performance: • 1.8V ± 0.1V Power Supply 1.8 V ± 0.1V (SSTL_18) compatible) I/O • DRAM organisations with 4, 8 and 16 data in/outputs • Double Data Rate architecture: two data transfers per clock cycle, four internal banks for concurrent operation •CAS Latency: 3, 4 and 5 • Burst Length: 4 and 8 Speed Sorts -5 DDR2 -400 -3.7 DDR2 -533 -3S DDR2 -667 -3 DDR2 -667 Units Bin (CL-tRCD-TRP) 3-3-3 4-4-4 5-5-5 4-4-4 tck max. Clock Frequency 200 266 333 MHz Data Rate 400 533 667 Mb/s/pin CAS Latency (CL) 3 4 5 4 tck tRCD 15 15 15 12 ns tRP 15151512 ns tRAS 40 45 45 45 ns tRC 55606057 ns • Differential clock inputs (CK and CK) • Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write data • DLL aligns DQ and DQS transitions with clock •DQS can be disabled for single-ended data strobe operation • Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS • Data masks (DM) for write data •Posted CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality. • Auto-Precharge operation for read and write bursts • Auto-Refresh, Self-Refresh and power saving Power- Down modes • Average Refresh Period 7.8µs at a TCASE lower than 85oC, 3.9µs between 85oC and 95oC • Normal and Weak Strength Data-Output Drivers • 1k page size • Lead-freePackages: 60 pin FBGA for x4 & x8 components 84 pin FBPA for x16 components 1.0 Description The 256Mb Double-Data-Rate-2 (DDR2) DRAMs are high- speed CMOS Double Data Rate 2 Synchronous DRAM devices containing 268,435,456 bits and are internally config- ured as a quad-bank DRAMs. The 256Mb chip is organized as either 16Mbit x 4 I/O x 4 bank, 8Mbit x 8 I/O x 4 bank or 4Mbit x 16 I/O x 4 bank device. These synchronous devices achieve high speed double-data-rate transfer rates of up to 667 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) normal and weak strength data- output driver, (4) Off-Chip Driver (OCD) impedance adjust- ment and (5) an ODT (On-Die Termination) function. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential (DQS, DQS) pair in a source synchronous fashion. A 15 bit address bus is used to con- vey row, column and bank address information in a RAS / CAS multiplexing style. The DDR2 devices operate with a 1.8V +/-0.1V power supply and are available in FBGA packages. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. . DATASHEET Rev. 1.02 (05.04) |
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