HYB25D256[800/160]BT(L)-[5/5A]

256MBit Double Data Rata SDRAM

2003-01-10, V0.9

Page 5 of 29

Block Diagram (32Mb x 8)

1

DQS

CK, CK

DLL

RAS

CAS

CK

CS

WE

CK

Column-Address

Counter/Latch

Mode

10

A0-A12,

BA0, BA1

CKE

15

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(8192 x 512x 16)

Sense Amplifiers

Bank1

Bank2

Bank3

13

9

1

2

2

8

8

8

Input

Register

1

1

1

1

1

16

16

2

16

clk

out

Data

Mask

Data

CK,

COL0

COL0

COL0

clk

in

DQS

Generator

8

8

8

8

8

16

DQ0-DQ7,

DM

DQS

1

Write

FIFO

&

Drivers

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of

the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-

rectional DQ and DQS signals.

Column

Decoder

512

(x16)

Registers

8192

13

CK