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C515 Datasheet(PDF) 10 Page - Infineon Technologies AG |
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C515 Datasheet(HTML) 10 Page - Infineon Technologies AG |
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10 / 55 page  C515 Semiconductor Group 10 1997-08-01 XTAL2 36 – XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. XTAL1 37 – XTAL1 Output of the inverting oscillator amplifier. P2.0-P2.7 38-45 I/O Port 2 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. PSEN 47 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods, except during external data memory accesses. The signal remains high during internal program execution. ALE 48 O The Address Latch enable output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods, except during an external data memory access. *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-80) I/O*) Function |
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