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SAFC164SM Datasheet(PDF) 9 Page - Infineon Technologies AG |
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SAFC164SM Datasheet(HTML) 9 Page - Infineon Technologies AG |
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9 / 68 page  C164CM C164SM Data Sheet 5 V1.0, 2001-05 Table 2 Pin Definitions and Functions Symbol Pin No. Input Outp. Function PORT0 P0H.7 P0H.6 P0H.5 P0H.4 P0H.3 P0H.2 P0H.1 P0H.0 P0L.7 P0L.6 P0L.5 P0L.4 P0L.3 P0L.2 P0L.1 P0L.0 8 9 10 11 12 13 14 15 18 19 20 21 22 23 24 25 IO (I)/O I/O (I)/O I/O (I)/O I/O (I)/O I/O (I)/O O (I)/O (I)/O (I)/O I/O I/O I/O I/O I/O I/O I/O I/O PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes. A(D)15 Most Significant Address(/Data) Line SCLK SSC Master Clock Output / Slave Clock Input. A(D)14 Address(/Data) Line MTSR SSC Master-Transmit/Slave-Receive Outp./Inp. A(D)13 Address(/Data) Line MRST SSC Master-Receive/Slave-Transmit Inp./Outp. A(D)12 Address(/Data) Line RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.) A(D)11 Address(/Data) Line TxD0 ASC0 Clock/Data Output (Async./Sync.) A(D)10 Address(/Data) Line A(D)9 Address(/Data) Line A(D)8 Address(/Data) Line AD7 Address/Data Line AD6 Address/Data Line AD5 Address/Data Line AD4 Address/Data Line AD3 Address/Data Line AD2 Address/Data Line AD1 Address/Data Line AD0 Least Significant Address/Data Line NMI 26 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C164CM into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. |
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