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TUSB2046BIRHBR Datasheet(PDF) 5 Page - Texas Instruments |
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TUSB2046BIRHBR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 28 page 5 TUSB2046B, TUSB2046BI www.ti.com SLLS413K – FEBRUARY 2000 – REVISED JANUARY 2016 Product Folder Links: TUSB2046B TUSB2046BI Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. OVRCUR1 10 I Overcurrent input. OVRCUR1–OVRCUR4 are active low. For per-port overcurrent detection, one overcurrent input is available for each of the four downstream ports. In the ganged mode, any OVRCUR input may be used and all OVRCUR terminals must be tied together. OVRCUR terminals are active low inputs with noise filtering logic. OVRCUR2 14 OVRCUR3 18 OVRCUR4 22 PWRON1 9 O Power-on/-off control signals. PWRON1–PWRON4 are active low, push-pull outputs. Push-pull outputs eliminate the pullup resistors which open-drain outputs require. However, the external power switches that connect to these terminals must be able to operate with 3.3-V inputs because these outputs cannot drive 5-V signals. PWRON2 13 PWRON3 17 PWRON4 21 RESET 4 I RESET is an active low TTL input with hysteresis and must be asserted at power up. When RESET is asserted, all logic is initialized. Generally, a reset with a pulse width between 100 μs and 1 ms is recommended after 3.3-V VCC reaches its 90%. Clock signal has to be active during the last 60 μs of the reset window. SUSPND 32 O Suspend status. SUSPND is an active high output available for external logic power-down operations. During the suspend mode, SUSPND is high. SUSPND is low for normal operation. TSTMODE 31 I Test/mode terminal. TSTMODE is used as a test terminal during production testing. This terminal must be tied to ground or 3.3-V VCC for normal 6-MHz or 48-MHz operation, respectively. TSTPLL/ 48MCLK 27 I/O Test/48-MHz clock input. TSTPLL/48MCLK is used as a test terminal during production testing. This terminal must be tied to ground for normal 6-MHz operation. If 48-MHz input clock is desired, a 48-MHz clock source (no crystal) can be connected to this input terminal. VCC 3, 25 3.3-V supply voltage XTAL1 30 I Crystal 1. XTAL1 is a 6-MHz crystal input with 50% duty cycle. An internal PLL generates the 48- MHz and 12-MHz clocks used internally by the ASIC logic. XTAL2 29 O Crystal 2. XTAL2 is a 6-MHz crystal output. This terminal must be left open when using an oscillator. (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage levels are with respect to GND. 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC Supply voltage(2) –0.5 3.6 V VI Input voltage range –0.5 VCC + 0.5 V VO Output voltage range –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 V or VI < VCC ±20 mA IOK Output clamp current VO < 0 V or VO < VCC ±20 mA TA Operating free-air temperature TUSB2046B 0 70 °C TUSB2046BI –40 85 Tstg Storage temperature range –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V Charged-device model (CDM), per JEDEC specification JESD22- C101(2) ±1500 |
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