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TPS65986ABZQZR Datasheet(PDF) 8 Page - Texas Instruments |
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TPS65986ABZQZR Datasheet(HTML) 8 Page - Texas Instruments |
8 / 109 page TPS65986 SLVSD13A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com 6.5 Power Supply Requirements and Characteristics Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT EXTERNAL VIN_3V3 Input 3.3-V supply 2.85 3.3 3.45 V Input voltage to power C_CC pins. This input is PP_CABLE also available to power core circuitry and the 2.95 5 5.5 V VOUT_3V3 output Bi-direction DC bus voltage. Output from the VBUS 4 5 22 V TPS65986 or input to the TPS65986 5V supply input to power VBUS. This supply does PP_5V0 4.75 5 5.5 V not power the TPS65986 VDDIO(1) Optional supply for I/O cells. 1.7 3.45 V INTERNAL DC 3.3V generated internally by either a switch VLDO_3V3 from VIN_3V3, an LDO from PP_CABLE, or an 2.7 3.3 3.45 V LDO from VBUS VDO_LDO3V3 Drop Out Voltage of LDO_3V3 from PP_CABLE ILOAD = 50 mA 250 mV Drop Out Voltage of LDO_3V3 from VBUS 250 500 750 mV VLDO_1V8D DC 1.8 V generated for internal digital circuitry 1.7 1.8 1.9 V VLDO_1V8A DC 1.8 V generated for internal analog circuitry 1.7 1.8 1.9 V DC voltage generated on LDO_BMC. Setting for VLDO_BMC 1.05 1.125 1.2 V USB-PD DC current supplied by the 3.3 V LDOs. This ILDO_3V3 includes internal core power and external load on 50 mA LDO_3V3. ILDO_3V3EX External DC current supplied by LDO_3V3 10 mA IOUT_3V3 External DC current supplied by VOUT_3V3 100 mA DC current supplied by LDO_1V8D. This is ILDO_1V8D intended for internal loads only but small external 50 mA loads may be added ILDO_1V8DEX External DC current supplied by LDO_1V8D 5 mA DC current supplied by LDO_1V8A. This is ILDO_1V8A intended for internal loads only but small external 20 mA loads may be added ILDO_1V8AEX External DC current supplied by LDO_1V8A 5 mA DC current supplied by LDO_BMC. This is ILDO_BMC 5 mA intended for internal loads only ILDO_BMCEX External DC current supplied by LDO_BMC 0 mA Forward voltage drop across VIN_3V3 to VFWD_DROP ILOAD = 50 mA 25 60 90 mV LDO_3V3 switch Input switch resistance from VIN_3V3 to RIN_3V3 VVIN_3V3 – VLDO_3V3 > 50 mV 0.5 1.1 1.75 Ω LDO_3V3 Output switch resistance from VIN_3V3 to ROUT_3V3 0.35 0.7 Ω VOUT_3V3 10% - 90% rise time on VOUT_3V3 from switch TR_OUT3V3 CVOUT_3V3 = 1 μF 35 120 µs enable (1) I/O buffers are not fail-safe to LDO_3V3. Therefore, VDDIO may power-up before LDO_3V3. When VDDIO powers up before LDO_3V3, the I/Os shall not be driven high. When VDDIO is low and LDO_3V3 is high, the I/Os may be driven high. 8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65986 |
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