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BTS6510 Datasheet(PDF) 2 Page - Infineon Technologies AG |
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BTS6510 Datasheet(HTML) 2 Page - Infineon Technologies AG |
2 / 15 page Data Sheet BTS6510 Page 2 of 15 2003-Oct-01 Pin Symbol Function 1 OUT O Output to the load. The pins 1,2,6 and 7 must be shorted with each other especially in high current applications! 3) 2 OUT O Output to the load. The pins 1,2,6 and 7 must be shorted with each other especially in high current applications!3) 3 IN I Input, activates the power switch in case of short to ground 4 Vbb + Positive power supply voltage, the tab is electrically connected to this pin. In high current applications the tab should be used for the Vbb connection instead of this pin 4). 5 IS S Diagnostic feedback providing a sense current proportional to the load current; zero current on failure (see Truth Table on page 6) 6 OUT O Output to the load. The pins 1,2,6 and 7 must be shorted with each other especially in high current applications!3) 7 OUT O Output to the load. The pins 1,2,6 and 7 must be shorted with each other especially in high current applications!3) Maximum Ratings at Tj = 25 °C unless otherwise specified Parameter Symbol Values Unit Supply voltage (overvoltage protection see page 4) Vbb 42 V Supply voltage for short circuit protection, Tj,start =-40 ...+150°C: (E AS limitation see diagram on page 9) Vbb 34 V Load current (short circuit current, see page 5) IL self-limited A Load dump protection VLoadDump = VA + Vs, VA = 13.5 V RI 5 ) = 2 Ω, RL = 0.54 Ω, td = 200 ms, IN, IS = open or grounded VLoad dump 6 ) 75 V Operating temperature range Storage temperature range Tj Tstg -40 ...+150 -55 ...+150 °C Power dissipation (DC), TC ≤ 25 °C Ptot 170 W Inductive load switch-off energy dissipation, single pulse Vbb = 12V, Tj,start = 150°C, TC = 150°C const., IL = 20 A, ZL = 7.5 mH, 0 Ω, (see diagrams on page 9 ) EAS 1.5 J Electrostatic discharge capability (ESD) Human Body Model acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993, C = 100 pF, R = 1.5 k Ω VESD 4kV Current through input pin (DC) Current through current sense status pin (DC) see internal circuit diagrams on page 7 IIN IIS +15 , -250 +15 , -250 mA 3 ) Not shorting all outputs will considerably increase the on-state resistance, reduce the peak current capability and decrease the current sense accuracy 4 ) Otherwise add about 0.3 m Ω to the RON if the pin is used instead of the tab. 5 ) RI = internal resistance of the load dump test pulse generator. 6 ) VLoad dump is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839. |
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