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M24C16-DRMF8TG Datasheet(PDF) 11 Page - STMicroelectronics |
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M24C16-DRMF8TG Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 39 page  DocID027242 Rev 1 11/39 M24C16-DRE Device operation 3.5 Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, as shown in Table 2 . The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device select code, the corresponding memory device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the memory device does not match the device select code, it deselects itself from the bus, and goes into Standby mode. Note: A: significant address bit. X: bit is Don’t Care. Table 2. Device select code Device type identifier (1) Chip Enable address RW b7 b6 b5 b4 b3 b2 b1 b0 When accessing the memory 1 0 1 0 A10 A9 A8 RW When accessing the identification page 101 1 X X X RW 1. The most significant bit, b7, is sent first. Table 3. Significant address bits Memory (Device type identifier = 1010b) Identification page (Device type identifier = 1011b) Random Address Read Write Read Identification page Write Identification page Lock Identification page Read lock status b3 (1) A10 A10 XXX see Section 4.2.5 b2 (1) A9 A9 X X X b1 (1) A8 A8 X X X b7 A7 A7 0 0 1 b6 A6 A6 X X X b5 A5 A5 X X X b4 A4 A4 X X X b3 A3 A3 A3 A3 X b2 A2 A2 A2 A2 X b1 A1 A1 A1 A1 X b0 A0 A0 A0 A0 X 1. Address bits defined inside the DeviceSelect code (see Table 2). |
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