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L6984ATR Datasheet(PDF) 4 Page - STMicroelectronics |
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L6984ATR Datasheet(HTML) 4 Page - STMicroelectronics |
4 / 34 page Pin settings L6984 4/34 DocID025378 Rev 3 1 Pin settings 1.1 Pin connection Figure 2. Pin connection (top view) 1.2 Pin description Table 1. Pin description No. Pin Description 1 PGOOD The open collector output is driven low when the FB voltage is below the VPGD L threshold (see Table 5). 2 FB Inverting input of the error amplifier 3 TON A resistor connected between this pin and VIN sets the switching frequency. 4EN Enable pin. A logical active high signal enables the device. Connect this pin to VIN if not used. 5 GND Power GND 6 LX Switching node 7 VIN DC input voltage 8VCC Embedded regulator output that supplies the main switching controller. Connect an external 1 F capacitor for proper operation. An integrated LDO regulates VCC = 3.3 V if VBIAS voltage is < 2.4 V. VCC is connected to VBIAS through a MOSFET switch if VBIAS > 3.2 V and the embedded LDO is disabled to increase the light load efficiency. 9 VBIAS Typically connected to the regulated output voltage. An external voltage reference can be used to supply the analog circuitry to increase the efficiency at light load. Connect to GND if not used. 10 LNM Connect to VCC for low noise mode (LNM) / to GND for low consumption mode (LCM) operation. |
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