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DS90UH948TNKDRQ1 Datasheet(PDF) 6 Page - Texas Instruments |
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DS90UH948TNKDRQ1 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 91 page  6 DS90UH948-Q1 SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016 www.ti.com Product Folder Links: DS90UH948-Q1 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Pin Functions (continued) PIN I/O, TYPE DESCRIPTION NAME NUMBER PDB 48 I, LVCMOS Configuration Pin w/ weak internal PD Power-Down Mode Input Pin PDB = 1, device is enabled (normal operation) PDB = 0, device is powered down. When the device is in the POWER DOWN state, the LVCMOS outputs are in tri-state, the PLL is shutdown and IDD is minimized. Note: PDB pin requires minimum ramp time of 200us BISTEN 5 I, LVCMOS Configuration Pin w/ weak internal PD Bist Enable Pin 0: BIST Mode is disabled. 1: BIST Mode is enabled. See Built-In Self Test (BIST) for more information BISTC (INTB_IN) 4 I, LVCMOS Configuration Pin w/ weak internal PD Bist Clock Select. 0: PCLK 1: 33MHz (Pin is shared with INTB_IN) INTB_IN (BISTC) 4 I, LVCMOS w/ weak internal PD Interrupt input. (Pin is shared with BISTC) BIDIRECTIONAL CONTROL CHANNEL (BCC) GPIO PINS (default pin function) - Layout note: for unused GPIO(s), tie to an external pulldown GPIO0 (SDOUT) 7 Multi-function pin I/O, LVCMOS BCC GPIO0. default state: logic LOW (Pin is shared with SDOUT) GPIO1 (SWC) 8 Multi-function pin I/O, LVCMOS BCC GPIO1. default state: logic LOW (Pin is shared with SWC) GPIO2 (I2S_DC) 10 Multi-function pin I/O, LVCMOS BCC GPIO2. default state: logic LOW (Pin is shared with I2S_DC) GPIO3 (I2S_DD) 9 Multi-function pin I/O, LVCMOS BCC GPIO3. default state: logic LOW (Pin is shared with I2S_DD) HIGH-SPEED GPIO PINS HIGH-SPEED GPIO PINS (default pin function) - Layout note: for unused D_GPIO(s), tie to an external pulldown D_GPIO0 (MOSI) 19 I/O, LVCMOS General Purpose I/O in 2-lane FPD-Link III mode default state: tri-state (Pin is shared with MOSI) D_GPIO1 (MISO) 18 I/O, LVCMOS General Purpose I/O in 2-lane FPD-Link III mode default state: tri-state (Pin is shared with MISO) D_GPIO2 (SPLK) 17 I/O, LVCMOS General Purpose I/O in 2-lane FPD-Link III mode default state: tri-state (Pin is shared with SPLK) D_GPIO3 (SS) 16 I/O, LVCMOS General Purpose I/O in 2-lane FPD-Link III mode default state: tri-state (Pin is shared with SS) REGISTER READ/WRITES ONLY GPIO PINS (default pin function) - Layout note: for unused GPIO(s), tie to an external pulldown GPIO5_REG (I2S_DB) 11 Multi-function pin I/O, LVCMOS General Purpose Input/Output 5 I2C register control only. default state: logic LOW (Pin is shared with I2S_DB) GPIO6_REG (I2S_DA) 12 Multi-function pin I/O, LVCMOS General Purpose Input/Output 6 I2C register control only. default state: logic LOW (Pin is shared with I2S_DA) |
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