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DS90CR286ATDGGQ1 Datasheet(PDF) 7 Page - Texas Instruments |
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DS90CR286ATDGGQ1 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 29 page LVCMOS Output DS90CR286AT-Q1 www.ti.com SNLS498A – NOVEMBER 2015 – REVISED DECEMBER 2015 Switching Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RCCD RxCLK IN to RxCLK OUT Delay at 25°C, 3.5 5.0 7.5 ns VCC = 3.3V (1) (Figure 4) RPLLS Receiver Phase Lock Loop Set (Figure 5) 10 ms RPDD Receiver Power Down Delay (Figure 7) 1 μs (1) Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency for the DS90CR285 transmitter and DS90CR286AT-Q1 receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period. If another transmitter is used, the alternative transmitter's TCCD must be used to calculate total latency. Figure 1. "Worst Case" Test Pattern Figure 2. LVCMOS Output Load and Transition Times Figure 3. Setup/Hold and High/Low Times Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DS90CR286AT-Q1 |
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