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DAC8162SQDGSRQ1 Datasheet(PDF) 3 Page - Texas Instruments |
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DAC8162SQDGSRQ1 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 54 page  V A OUT V B OUT GND LDAC CLR 1 2 3 4 5 6 7 8 9 10 SYNC SCLK D IN AV DD V /V REFIN REFOUT DAC7562-Q1, DAC7563-Q1 DAC8162-Q1, DAC8163-Q1 DAC8562-Q1, DAC8563-Q1 www.ti.com SLAS950A – MAY 2013 – REVISED JUNE 2015 5 Device Comparison Table MAXIMUM RELATIVE MAXIMUM DIFFERENTIAL MAXIMUM REFERENCE PART NUMBER RESOLUTION RESET TO ACCURACY (LSB) NONLINEARITY (LSB) DRIFT (ppm/°C) DAC7562-Q1 Zero 12-bit ±0.75 ±0.25 10 DAC7563-Q1 Mid-scale DAC8162-Q1 Zero 14-bit ±3 ±0.5 10 DAC8163-Q1 Mid-scale DAC8562-Q1 Zero 16-bit ±12 ±1 10 DAC8563-Q1 Mid-scale 6 Pin Configuration and Functions DGS Package 10-Pin VSSOP Top View Pin Functions PIN DESCRIPTION NAME NO. AVDD 9 Power-supply input, 2.7 V to 5.5 V Asynchronous clear input. The CLR input is falling-edge sensitive. When CLR is activated, zero scale (DACxx62- Q1) or mid-scale (DACxx63-Q1) is loaded to all input and DAC registers. This sets the DAC output voltages CLR 5 accordingly. The part exits clear code mode on the 24th falling edge of the next write to the part. If CLR is activated during a write sequence, the write is aborted. Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock input. DIN 8 Schmitt-trigger logic input GND 3 Ground reference point for all circuitry on the device In synchronous mode, data are updated with the falling edge of the 24th SCLK cycle, which follows a falling edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND permanently or asserted and held low before sending commands to the device. LDAC 4 In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous DAC updates. Multiple single-channel commands can be written in order to set different channel buffers to desired values and then make a falling edge on LDAC pin to simultaneously update the DAC output registers. SCLK 7 Serial clock input. Data can be transferred at rates up to 50 MHz. Schmitt-trigger logic input Level-triggered control input (active-low). This input is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The SYNC 6 DAC output updates following the 24th clock falling edge. If SYNC is taken high before the 23rd clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC756x-Q1, DAC816x-Q1, DAC856x-Q1. Schmitt-trigger logic input VOUTA 1 Analog output voltage from DAC-A VOUTB 2 Analog output voltage from DAC-B VREFIN/VREFOUT 10 Bidirectional voltage reference pin. If internal reference is used, 2.5-V output. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DAC7562-Q1 DAC7563-Q1 DAC8162-Q1 DAC8163-Q1 DAC8562-Q1 DAC8563-Q1 |
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