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ADC12D1000CIUT Datasheet(PDF) 11 Page - Texas Instruments |
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ADC12D1000CIUT Datasheet(HTML) 11 Page - Texas Instruments |
11 / 86 page VDR DR GND + - + - VDR DR GND + - + - ADC12D1000, ADC12D1600 www.ti.com SNAS480N – MAY 2010 – REVISED AUGUST 2015 Pin Functions: High-Speed Digital Outputs PIN I/O EQUIVALENT CIRCUIT DESCRIPTION NAME NO. Data Clock Output for the I- and Q-channel data bus. These differential clock outputs are used to latch the output data and, if used, should always be terminated with a 100- Ω differential resistor placed as closely as possible to the differential receiver. Delayed and non-delayed data outputs are supplied DCLKI+/- K19/K20 O synchronously to this signal. In 1:2 Demux Mode or DCLKQ+/- L19/L20 Non-Demux Mode, this signal is at ¼ or ½ the sampling clock rate, respectively. DCLKI and DCLKQ are always in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST to become synchronized. DI11+/- J18/J19 DI10+/- H19/H20 DI9+/- H17/H18 DI8+/- G19/G20 DI7+/- G17/G18 DI6+/- F18/F19 DI5+/- E19/E20 I- and Q-channel Digital Data Outputs. In Non- DI4+/- D19/D20 Demux Mode, this LVDS data is transmitted at the DI3+/- D18/E18 sampling clock rate. In Demux Mode, these outputs DI2+/- C19/C20 provide ½ the data at ½ the sampling clock rate, DI1+/- B19/B20 synchronized with the delayed data, that is, the DI0+/- B18/C17 other ½ of the data which was sampled one clock · · O cycle earlier. Compared with the DId and DQd DQ11+/- M18/M19 outputs, these outputs represent the later time DQ10+/- N19/N20 samples. If used, each of these outputs should DQ9+/- N17/N18 always be terminated with a 100- Ω differential DQ8+/- P19/P20 resistor placed as closely as possible to the DQ7+/- P17/P18 differential receiver. DQ6+/- R18/R19 DQ5+/- T19/T20 DQ4+/- U19/U20 DQ3+/- U18/T18 DQ2+/- V19/V20 DQ1+/- W19/W20 DQ0+/- W18/V17 Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ADC12D1000 ADC12D1600 |
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