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RPC56EL60L5BFQY Datasheet(PDF) 11 Page - STMicroelectronics |
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RPC56EL60L5BFQY Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 137 page DocID026934 Rev 1 11/137 RPC56EL60L5 Introduction 136 High-performance e200z4d dual core – 32-bit Power Architecture® technology CPU – Core frequency as high as 120 MHz – Dual issue five-stage pipeline core – Variable Length Encoding (VLE) – Memory Management Unit (MMU) – 4 KB instruction cache with error detection code – Signal processing engine (SPE) Memory available – 1 MB flash memory with ECC – 128 KB on-chip SRAM with ECC – Built-in RWW capabilities for EEPROM emulation SIL3/ASILD innovative safety concept: LockStep mode and Fail-safe protection – Sphere of replication (SoR) for key components (such as CPU core, eDMA, crossbar switch) – Fault collection and control unit (FCCU) – Redundancy control and checker unit (RCCU) on outputs of the SoR connected to FCCU – Boot-time Built-In Self-Test for Memory (MBIST) and Logic (LBIST) triggered by hardware – Boot-time Built-In Self-Test for ADC and flash memory triggered by software – Replicated safety enhanced watchdog – Replicated junction temperature sensor – Non-maskable interrupt (NMI) – 16-region memory protection unit (MPU) – Clock monitoring units (CMU) – Power management unit (PMU) – Cyclic redundancy check (CRC) unit Decoupled Parallel mode for high-performance use of replicated cores Nexus Class 3+ interface Interrupts – Replicated 16-priority controller – Replicated 16-channel eDMA controller GPIOs individually programmable as input, output or special function Three 6-channel general-purpose eTimer units 2 FlexPWM units – Four 16-bit channels per module Communications interfaces – 2 LINFlexD channels – 3 DSPI channels with automatic chip select generation – 2 FlexCAN interfaces (2.0B Active) with 32 message objects |
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