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ADS8557IPM Datasheet(PDF) 5 Page - Texas Instruments |
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ADS8557IPM Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 47 page  5 ADS8556, ADS8557, ADS8558 www.ti.com SBAS404D – OCTOBER 2006 – REVISED FEBRUARY 2016 Product Folder Links: ADS8556 ADS8557 ADS8558 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1) DB2/SEL_C 15 DIO, DI Word mode (WORD/BYTE = 0): Data bit 2 input/output Select SDO_C input. When high, SDO_C is active. When low, SDO_C is disabled. Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD DB1/SEL_B 16 DIO, DI Word mode (WORD/BYTE = 0): Data bit 1 input/output Select SDO_B input. When high, SDO_B is active. When low, SDO_B is disabled. Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD DB0/SEL_A 17 DIO, DI Word mode (WORD/BYTE = 0): Data bit 0 (LSB) input/output Select SDO_A input. When high, SDO_A is active. When low, SDO_A is disabled. Must always be high. Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD BUSY/INT 18 DO When CR bit C21 = 0 (BUSY/INT), converter busy status output. Transitions high when a conversion has been started and remains high during the entire process. Transitions low when the conversion data of all six channels are latched to the output register and remains low thereafter. In sequential mode (SEQ = 1 in the CR), the BUSY output transitions high when a conversion has been started and goes low for a single conversion clock cycle (tCCLK) whenever a channel pair conversion is completed. When bit C21 = 1 (BUSY/INT in CR), interrupt output. This bit transitions high after a conversion completes and remains high until the conversion result is read. The polarity of BUSY/INT output can be changed using bit C20 (BUSY L/H) in the control register. CS/FS 19 DI, DI Chip select input. When low, the parallel interface is enabled. When high, the interface is disabled. Frame synchronization. The falling edge of FS controls the frame transfer. RD 20 DI Read data input. When low, the parallel data output is enabled. When high, the data output is disabled. Connect to BGND. CONVST_C 21 DI Hardware mode (HW/SW = 0): Conversion start of channel pair C. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_C[1:0]. CONVST_C must remain high during the entire conversion cycle, otherwise both ADCs of channel C are put in partial power-down mode (see the Reset and Power-Down Modes section). Software mode (HW/SW = 1): Conversion start of channel pair C in sequential mode (CR bit C23 = 1) only; connect to BGND or BVDD otherwise. CONVST_B 22 DI Hardware mode (HW/SW = 0): Conversion start of channel pair B. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_B[1:0]. CONVST_B must remain high during the entire conversion cycle; otherwise, both ADCs of channel B are put into partial power-down mode (see the Reset and Power-Down Modes section). Software mode (HW/SW = 1): Conversion start of channel pair B in sequential mode (CR bit C23 = 1) only; connect to BGND or BVDD otherwise. CONVST_A 23 DI Hardware mode (HW/SW = 0): Conversion start of channel pair A. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_A[1:0]. CONVST_A must remain high during the entire conversion cycle; otherwise, both ADCs of channel A are put into partial power-down mode (see the Reset and Power-Down Modes section). Software mode (HW/SW = 1): Conversion start of all selected channels except in sequential mode (CR bit C23 = 1): Conversion start of channel pair A only. STBY 24 DI Standby mode input. When low, the entire device is powered-down (including the internal clock and reference). When high, the device operates in normal mode. AGND 25, 32, 37, 38, 43, 44, 49, 52, 53, 55, 57, 59 P Analog ground, connect to analog ground plane Pin 25 can have a dedicated ground if the difference between its potential and AGND is always kept within ±300 mV. |
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