ADS1000-Q1

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SBAS480B – SEPTEMBER 2009 – REVISED OCTOBER 2015

Device Functional Modes (continued)

7.4.2 Reset and Power Up

When the ADS1000-Q1 powers up, it automatically performs a reset. As part of the reset, the ADS1000-Q1 sets

all of the bits in the configuration register to their respective default settings.

Call Reset, it performs an internal reset, exactly as though it had just been powered on.

7.5 Programming

drive the bus lines low, by connecting them to ground; they never drive the bus lines high. Instead, the bus wires

are pulled high by pullup resistors, so the bus wires are high when no device is driving them low. This way, two

devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of

while SCL is low (a Low on SDA indicates the bit is 0; a High indicates the bit is 1). Once the SDA line has

settled, the SCL line is brought high, then low. This pulse on SCL clocks the SDA bit into the receiver shift

register.

from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. The

master always drives the clock line. The ADS1000-Q1 never drives SCL, because it cannot act as a master. On

the ADS1000-Q1, SCL is an input only.

Most of the time the bus is idle, no communication takes place, and both lines are high. When communication

takes place, the bus is active. Only master devices can start a communication. They do this by causing a start

condition on the bus. Normally, the data line is only allowed to change state while the clock line is low. If the data

line changes state while the clock line is high, it is either a start condition or its counterpart, a stop condition. A

start condition is when the clock line is high and the data line goes from high to low. A stop condition is when the

clock line is high and the data line goes from low to high.

After the master issues a start condition, it sends a byte that indicates with which slave device it wants to

sends an address in the address byte, together with a bit that indicates whether it wishes to read from or write to

the slave device.

When a master has finished sending a byte, eight data bits, to a slave, it stops driving SDA and waits for the

slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA low. The master then sends a

clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA low

to acknowledge to the slave that it has finished reading the byte. It then sends a clock pulse to clock the bit.

(Remember that the master always drives the clock line.)

A not-acknowledge is performed by simply leaving SDA high during an acknowledge cycle. If a device is not

present on the bus, and the master attempts to address it, it will receive a not-acknowledge because no device is

present at that address to pull the line low.

When a master has finished communicating with a slave, it may issue a stop condition. When a stop condition is

issued, the bus becomes idle again. A master may also issue another start condition. When a start condition is

issued while the bus is active, it is called a repeated start condition.

parameters for this diagram.

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