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TS7003ITD833 Datasheet(PDF) 9 Page - Silicon Laboratories |
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TS7003ITD833 Datasheet(HTML) 9 Page - Silicon Laboratories |
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9 / 15 page  TS7003 TS7003 Rev. 1.0 Page 9 process, the input side of CHOLD is switched back to AIN so as to be charged to the input signal again. An ADC’s acquisition time is function of how fast its input capacitance can be charged. If an input signal’s driving-point source impedance is high, the acquisition time is lengthened and more time must be allowed between conversions. The acquisition time (tACQ) is the maximum time the ADC requires to acquire the signal and is also the minimum time needed for the signal to be acquired. The TS7003’s acquisition time is calculated from the following expression: tACQ = 9 x (RS + RIN) x 10pF where RIN = 100 Ω (the TS7003’s internal track/hold switch resistance), RS = the input signal’s source impedance, and tACQ is never less than 625ns. Because of the input structure of the TS7003, sources with output impedances of 1k Ω or less do not affect significantly the AC performance of the TS7003. The TS7003 can still be used in applications where the source impedance is higher so long as a 0.01 μF capacitor is connected between the analog input and GND. Limiting the ADC’s input signal bandwidth, the use of an external, input capacitor forms an RC filter with the input’s source impedance. Input Bandwidth Considerations Since the TS7003’s input track-and-hold circuit exhibits a 10 MHz small-signal bandwidth, it is possible to measure periodic signals and to digitize high-speed transient events with signal bandwidths higher than the TS7003’s sampling rate by using undersampling techniques. To avoid the aliasing of high-frequency signals into the frequency band of interest, the use of external anti-alias filter circuits (discrete or integrated) is recommended. The time constant of the external anti-alias filter should be set so as not to interfere with the desired signal bandwidth. Analog Input Protection The TS7003 incorporates internal protection diodes that clamp the analog input between VDD and GND. These internal protection diodes allow the AIN pin to swing from GND - 0.3V to VDD + 0.3V without causing damage to the TS7003. However, for accurate conversions near full scale, the input signal must not exceed VDD by more than 50mV or be lower than GND by 50mV. If the analog inputs can exceed 50mV beyond the supplies, then the current in the forward-biased protection diodes should be limited to less than 2mA since large fault currents can affect conversion results. Internal Reference Considerations The TS7003 has an internal voltage reference that is factory-trimmed to 2.5V. The internal reference output is connected to the REF pin and is also connected to the ADC’s internal CDAC. The REF output can be used as a reference voltage source for other components external to the ADC and can source up to 750 μA. To maintain conversion accuracy to within 1 LSB, a 4.7 μF capacitor from the REF pin to GND is recommended. While larger-valued capacitors can be used to further reduce reference wide-band noise, larger capacitor values can increase the TS7003’s wake-up time when exiting from shutdown mode (see the “Using SHDN to Reduce Operating Supply Current” section for more information). When in shutdown (that is, when SHDN = 0), the TS7003’s internal 2.5-V reference is disabled. Serial Digital Interface Initialization after Power-Up and Starting a Conversion If the SHDN pin is not driven low upon an initial, cold- start condition, it may take up to 2.5ms for a fully- discharged 4.7 μF reference bypass capacitor to provide adequate charge for specified conversion accuracy. As a result, conversions should not be initiated during this reference capacitor charge-up delay. To initiate a conversion, the CS pin is toggled (or driven) low. At the CS’s falling edge, the TS7003’s internal track-and-hold is placed in hold mode and a conversion is initiated. Data can then be transferred out of the ADC using an external serial clock. |
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