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M37702M2A-278FP Datasheet(PDF) 7 Page - Mitsubishi Electric Semiconductor |
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M37702M2A-278FP Datasheet(HTML) 7 Page - Mitsubishi Electric Semiconductor |
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7 / 59 page  7 MITSUBISHI MICROCOMPUTERS M37702M2AXXXFP, M37702M2BXXXFP M37702S1AFP, M37702S1BFP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CENTRAL PROCESSING UNIT (CPU) The CPU has ten registers and is shown in Figure 3. Each of these registers is described below. ACCUMULATOR A (A) Accumulator A is the main register of the microcomputer. It con- sists of 16 bits and the lower 8 bits can be used separately. The data length flag m determines whether the register is used as 16- bit register or as 8-bit register. It is used as a 16-bit register when flag m is “0” and as an 8-bit register when flag m is “1”. Flag m is a part of the processor status register (PS) which is described later. Data operations such as calculations, data transfer, input/output, etc., is executed mainly through the accumulator. ACCUMULATOR B (B) Accumulator B has the same functions as accumulator A, but the use of accumulator B requires more instruction bytes and execu- tion cycles than accumulator A. INDEX REGISTER X (X) Index register X consists of 16 bits and the lower 8 bits can be used separately. The index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag x is “0” and as an 8-bit reg- ister when flag x is “1”. Flag x is a part of the processor status reg- ister (PS) which is described later. In index addressing mode, register X is used as the index register and the contents of this address is added to obtain the real ad- dress. Also, when executing a block transfer instruction MVP or MVN, the contents of index register X indicate the low-order 16 bits of the source data address. The third byte of the MVP and MVN is the high-order 8 bits of the source data address. INDEX REGISTER Y (Y) Index register Y consists of 16 bits and the lower 8 bits can be used separately. The index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag x is “0” and as an 8-bit reg- ister when flag x is “1”. Flag x is a part of the processor status register (PS) which is described later. In index addressing mode, register Y is used as the index register and the contents of this address is added to obtain the real ad- dress. Also, when executing a block transfer instruction MVP or MVN, the contents of index register Y indicate the low-order 16 bits of the destination address. The second byte of the MVP and MVN is the high-order 8 bits of the destination data address. Fig. 3 Register structure 70 PG Program bank register PG 70 DT Data bank register DT Carry flag Zero flag Interrupt disable flag Decimal mode flag Index register length flag Data length flag Negative flag Overflow flag Processor interrupt priority level IPL Accumulator A Accumulator B Index register X Index register Y Stack pointer S Program counter PC Direct page register DPR Processor status register PS 0 AH AL 15 0 7 BH BL 15 0 7 XH XL 15 0 7 YH YL 15 0 7 15 0 PC 15 0 15 0 DPR 7 15 0 N IPL2 IPL0 IPL1 C Z I D x m V 00 00 S |
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